JPH02105566A - Complementary semiconductor device - Google Patents

Abstract

PURPOSE:To perform stable movements and allow a transistor to be improved in performances by installing wells having highly concentrated buried layers as bases at a boundary region between a first conductivity type semiconductor substrate and a second conductivity type epitaxial layer, thereby mounting a transistor. CONSTITUTION:Two regions of the first conductivity type wells 8 and 9 which selectively have highly concentrated first and second conductivity type buried layers 5' and 4' as respective bases of the foregoing wells at a boundary region between the first conductivity type semiconductor substrate 1 and the second conductivity type epitaxial layer 6 are installed and the second conductivity type transistors are mounted on respective wells 8 and 9. Consequently, the first well 8 which is electrically insulated from the substrate 1 and has the same conductivity type as that of the substrate 1 is formed and then, a current flowing in the first well does not change into a substrate current. As the potential of the substrate 1 does not sway, such a state electric potential allows a transistor to perform stable movements and to be highly efficient partially as well.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to complementary semiconductor devices, and particularly to CMO8 semiconductor devices.

[Conventional technology]

As shown in FIG. 2, in the conventional CMO3 semiconductor device, a well (18) is formed by diffusing impurities of the opposite conductivity type to the substrate onto the surface of the silicon substrate, and a well (18) is formed on the surface of the silicon substrate where the well is not formed. A transistor of conductivity type opposite to the substrate,
A transistor of the same conductivity type as the substrate is formed in the region where the well is formed.

[Problem to be solved by the invention]

However, in the conventional structure described above, the substrate potential of the substrate and the transistors of the opposite conductivity type are all the same, so when a voltage is applied to the diffusion layer junction in the forward direction with respect to the substrate, a substrate current flows. This has disadvantages in that the potential of the substrate fluctuates, the data in the memory cell is destroyed, and the latch-already 1 phenomenon peculiar to OMO3 occurs. Another drawback is that a different substrate potential cannot be applied to a transistor of the opposite conductivity type to the substrate, even when changing the substrate potential to reduce the junction capacitance or to improve the performance of the transistor without increasing the surface impurity concentration. was there.

FIG. 3 shows an example of an input protection circuit in which the substrate current flows. If noise lower than the GND level enters the input, the junction of the diffusion layer will be in the forward direction and a current will flow through the substrate.

An object of the present invention is to provide a complementary semiconductor device that can operate stably and has excellent performance.

[Means to solve the problem]

The complementary semiconductor device of the present invention includes a high concentration buried layer of a first conductivity type selectively provided in a boundary region between a semiconductor substrate of a first conductivity type and an epitaxial layer of a second conductivity type formed thereon; It has a second first conductivity type well and a first first conductivity type well each having a high concentration buried layer of the second conductivity type as a bottom surface, and a transistor of the second conductivity type is provided in each of the wells. There is.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(h) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention along its manufacturing process.

As shown in FIG. 1 (a), for example, a P-type silicon substrate 1
A silicon oxide film 2 is grown thereon to a thickness of 50 nm, and then a photoresist mask 3-1 is provided and an N-type impurity region 4 is formed on the silicon substrate surface by selective ion implantation of, for example, arsenic. The implantation conditions were a dose of 1. OX10
16 cm-2 and an acceleration voltage of 100 kV.

Next, as shown in FIG. 1(b), a photoresist mask 3
-2, and a P-type impurity region 5 is formed on the silicon substrate surface by selective ion implantation of, for example, boron. The implantation conditions were a dose of 5 x 50"cm-2 and an acceleration voltage of 50k.
It is V.

After that, as shown in FIG. 1(C), the silicon oxide film 2 is
After removing, an N-type epitaxial layer 6 of silicon is grown on the entire surface.

Next, as shown in FIG. 1(d), a silicon oxide film 7 is formed on the surface of the epitaxial layer, and a photoresist mask 3-
3 is provided, and an impurity of the same conductivity type as the substrate, such as boron, is selectively ion-implanted to form a first P-type layer having a heavily doped N-type buried layer 4' and a heavily doped P-type buried layer 5' as its bottom. A well and a second P well 9 are formed. At this time, the first P well 8
is surrounded by a heavily doped N-type buried layer 4' and an N-type epitaxial layer 6 and is therefore electrically insulated from the P-type silicon substrate 1; It will be electrically connected to the P-type silicon substrate 1 through the layer 5'.

Next, as shown in FIG. 1(e), a field oxide film 10 is formed by the usual selective oxidation method, polycrystalline silicon is grown, and three patternings are performed to form polycrystalline silicon gates 11-1. ... to form.

Next, as shown in FIG. 1(f), a photoresist mask 3-4 is provided and an impurity having a conductivity type opposite to that of the substrate, such as arsenic, is implanted to form an N+ diffusion which will become the source/train region of the N-channel MO transistor. Layer 12-1. . . . and an N+ diffusion layer 13 which becomes an electrode lead region of the epitaxial silicon layer is formed.

Next, as shown in FIG. 1(g), a photoresist mask 3-5 is provided and an impurity having the same conductivity type as the substrate, such as boron, is implanted to form the source of the P-channel MO8)-transistor.
P+ diffusion layer 14-1, 14-2 serving as a train region and P+ diffusion layer 1 serving as an electrode extraction region of the second P well 8
form 5.

Thereafter, as shown in FIG. 1(h), an interlayer insulating film, such as a CVD oxide film 16, is formed, contacts are opened, and aluminum interconnections 17 are provided, thereby obtaining the desired structure.

Note that the concentration of the high concentration N-type buried layer 4' is approximately 1.0Xl.
() 19c, -3, the thickness is about 2.0 μm, and the concentration of the high concentration P-type buried layer 5' is about 5. OX 10 "cm-', thickness is approximately 1.5 μm.

In this embodiment, a P-type silicon substrate was used as an example;
The same applies to the type silicon substrate, and also as shown in Fig. 1(d).
), as shown in FIG. 1(d'), an impurity having a conductivity type opposite to that of the substrate, such as phosphorus, is implanted around the first P well 8 to form an N well 18. The electrical isolation of the P well 8 can be further ensured, and the threshold voltage of the P channel MOS transistor can also be adjusted.

1st. The second P-wells are electrically isolated from each other to prevent mutual interference and to ensure that their respective bias voltages (
Since the substrate potentials do not have to be the same, performance can be improved.

〔Effect of the invention〕

As explained above, in the present invention, since the first well is formed which is electrically insulated from the substrate and has the same conductivity type as the substrate, the current flowing through the first well does not become the substrate current. It is possible to operate stably without fluctuations in the potential of the transistor, and it is also possible to change the substrate potential of a transistor of a conductivity type opposite to that of the substrate, which has the effect of partially improving the performance of the transistor.

[Brief explanation of the drawing]

1(a) to 1(h) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention along its manufacturing process;
Figure (d) is a cross-sectional view of a semiconductor chip for explaining a modification of one embodiment, Figure 2 is a cross-sectional view of a semiconductor chip showing a conventional CMO8 semiconductor device, and Figure 3 is a cross-sectional view of a semiconductor chip showing a conventional CMO8 semiconductor device. FIG. 3 is a circuit diagram of an input protection circuit showing an example where the substrate current flows in the forward direction. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2, 7... Silicon oxide film, 3-1 to 3-5... Photoresist mask, 4...
・N-type impurity diffusion region, 4'...high concentration N-type buried layer,
... P type impurity diffusion region, 5'... High concentration P type buried layer, 6... N type epitaxial layer, 8... First P type
well, 9... second P well, 10... field oxide film, 11-1 to 11-3... polycrystalline silicon gate, 12-1 to 12-4.13... N+ diffusion layer ,1
4-1.14-2.15...P+ diffusion layer, 16...
CVD oxide film, 17... Aluminum wiring, 18...
・N well, Tr 1, Tr 3...N channel MOS transistor, Tr2...P channel MO
S transistor.

Claims (1)

[Claims] A high concentration buried layer of the first conductivity type and a buried layer of the high concentration second conductivity type are selectively provided in the boundary region between the first conductivity type semiconductor substrate and the second conductivity type epitaxial layer formed thereon. A complementary semiconductor comprising a second well of the first conductivity type and a first well of the first conductivity type, each of which has a bottom surface, and a transistor of the second conductivity type is provided in each of the wells. Device.