JPH03120148U - - Google Patents

Info

Publication number
JPH03120148U
JPH03120148U JP2774990U JP2774990U JPH03120148U JP H03120148 U JPH03120148 U JP H03120148U JP 2774990 U JP2774990 U JP 2774990U JP 2774990 U JP2774990 U JP 2774990U JP H03120148 U JPH03120148 U JP H03120148U
Authority
JP
Japan
Prior art keywords
data
output
input
signal
sent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2774990U
Other languages
Japanese (ja)
Other versions
JPH0756519Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2774990U priority Critical patent/JPH0756519Y2/en
Publication of JPH03120148U publication Critical patent/JPH03120148U/ja
Application granted granted Critical
Publication of JPH0756519Y2 publication Critical patent/JPH0756519Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Information Transfer Systems (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Communication Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す回路図、第2
図は相手装置が入力機器であるときの通信手順を
示すタイミングチヤート、第3図は相手装置が出
力機器であるときの通信手順を示すタイミングチ
ヤート、第4図はデータ通信装置の従来例を示し
た回路図、である。 符号の説明、1……CPU、2……通信装置、
3……出力ラツチ、4……入力バツフア、11〜
13……出力ラツチ、15,16……インバータ
、17〜19……AND素子、24……ストロー
ブ信号の送受信回路、25……ビジー信号の送受
信回路、26……アクノリツジ信号の送受信回路
、27……データの送受信回路、28……グラン
ド端子、29……入出力切換信号端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a timing chart showing the communication procedure when the other device is an input device, FIG. 3 is a timing chart showing the communication procedure when the other device is an output device, and FIG. 4 shows a conventional example of a data communication device. This is the circuit diagram. Explanation of symbols, 1...CPU, 2...Communication device,
3...Output latch, 4...Input buffer, 11~
13... Output latch, 15, 16... Inverter, 17-19... AND element, 24... Strobe signal transmitting/receiving circuit, 25... Busy signal transmitting/receiving circuit, 26... Acknowledge signal transmitting/receiving circuit, 27... ...Data transmission/reception circuit, 28...Ground terminal, 29...Input/output switching signal terminal.

Claims (1)

【実用新案登録請求の範囲】 第1の装置と第2の装置との間でハンドシエイ
ク信号を伴つてデータを送受信するデータ通信装
置において、 第1の装置から第2の装置へ向けてデータを出
力するための出力ラツチと、第2の装置から第1
の装置へデータを入力させるための入力バツフア
と、を共通のデータ通信路に並列に接続すると共
に、第1の装置から第2の装置へ向けてデータを
出力する通信モードなのか、第2の装置から第1
の装置へデータを入力する通信モードなのか、を
その信号レベルによつて示す入出力切換信号を第
2の装置から第1の装置へ送出して該第1の装置
に知らせるための信号線と、該信号線を介して送
出される前記入出力切換信号が第1のレベルにあ
るときは、第2の装置から第1の装置へハンドシ
エイク信号を送出することは許すが、その逆は阻
止することにより、前記入力バツフアを介して第
2の装置から第1の装置へのデータ送信を可能に
し、前記入出力切換信号が第2のレベルにあると
きは、第1の装置から第2の装置へハンドシエイ
ク信号を送出することは許すが、その逆は阻止す
ることにより、前記出力ラツチを介して第1の装
置から第2の装置へのデータ送信を可能にするゲ
ート回路と、を具備したことを特徴とするデータ
通信装置。
[Claims for Utility Model Registration] In a data communication device that transmits and receives data with a handshake signal between a first device and a second device, data is output from the first device to the second device. an output latch for connecting the second device to the first
Is it a communication mode in which an input buffer for inputting data to a second device is connected in parallel to a common data communication path, and data is output from the first device to a second device? 1st from the device
a signal line for transmitting an input/output switching signal from the second device to the first device to notify the first device whether the communication mode is for inputting data to the device; , when the input/output switching signal sent through the signal line is at a first level, the handshake signal is allowed to be sent from the second device to the first device, but the reverse is prevented. thereby enabling data transmission from the second device to the first device via the input buffer, and when the input/output switching signal is at a second level, the data transmission from the first device to the second device. a gate circuit that allows data to be transmitted from the first device to the second device through the output latch by allowing handshake signals to be sent to the device, but blocking the reverse; A data communication device characterized by:
JP2774990U 1990-03-20 1990-03-20 Data communication device Expired - Lifetime JPH0756519Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2774990U JPH0756519Y2 (en) 1990-03-20 1990-03-20 Data communication device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2774990U JPH0756519Y2 (en) 1990-03-20 1990-03-20 Data communication device

Publications (2)

Publication Number Publication Date
JPH03120148U true JPH03120148U (en) 1991-12-10
JPH0756519Y2 JPH0756519Y2 (en) 1995-12-25

Family

ID=31530589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2774990U Expired - Lifetime JPH0756519Y2 (en) 1990-03-20 1990-03-20 Data communication device

Country Status (1)

Country Link
JP (1) JPH0756519Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101400856B1 (en) * 2013-08-27 2014-05-29 김중호 Connecting tool for hanging

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101400856B1 (en) * 2013-08-27 2014-05-29 김중호 Connecting tool for hanging

Also Published As

Publication number Publication date
JPH0756519Y2 (en) 1995-12-25

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