JPH03120752A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JPH03120752A JPH03120752A JP1258205A JP25820589A JPH03120752A JP H03120752 A JPH03120752 A JP H03120752A JP 1258205 A JP1258205 A JP 1258205A JP 25820589 A JP25820589 A JP 25820589A JP H03120752 A JPH03120752 A JP H03120752A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- region
- well
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000000295 complement effect Effects 0.000 claims 2
- 239000010410 layer Substances 0.000 abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 241001494479 Pecora Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置及びその製造方法に関する。特に
、０Ｍ０８ＦＥＴが集積してなる高速大規模集積回路（
ＬＳＩ）において特に有効である［従来の技術」
従来の、０Ｍ０３ＦＥＴからなる半導体の断面図を第６
図に示す。基板６１には、Ｐウェル６２、ｎウェル５６
が形成され、Ｐウェル６２中にはゲート電極３６．ｎ＋
拡散層ソースドレイン３５からなるＰチャンネルＭＯＳ
ＦＥＴが存在している。ＬＳＩの高集積化に伴ない、例
えば、端子Ｂからの雑音電流があるレベルを超えると、
２つの寄生バイポーラトランジスタｐｒＬｐＴ２ 、ｎ
ＰｎＴ、が導通して、電源端子Ａから接地端子Ｂに定常
的な大電流が流れ、いわゆるラッチアップの不具合を発
生する。従来は、基板抵抗Ｒ１＋Ｒ２Ｒ３、Ｒ４の基板
抵抗の最適化によりラッチアソプを回避してきた。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, a high-speed large-scale integrated circuit (
[Conventional technology] Particularly effective in LSI) A cross-sectional view of a conventional semiconductor consisting of 0M03FET
As shown in the figure. The substrate 61 has a P well 62 and an N well 56.
are formed in the P-well 62, and a gate electrode 36. n+
P channel MOS consisting of diffusion layer source drain 35
FET exists. With the increasing integration of LSIs, for example, when the noise current from terminal B exceeds a certain level,
Two parasitic bipolar transistors prLpT2, n
PnT becomes conductive, and a steady large current flows from the power supply terminal A to the ground terminal B, causing a so-called latch-up problem. Conventionally, latch response has been avoided by optimizing the substrate resistance of substrate resistance R1+R2R3 and R4.
［発明が解決しようとする課題］
しかしながら、サブミクロンより微細化された０ＭＯ３
半導体装置ではラッチアップを生じる雑音電流のマージ
ンが無（ＬＳ Ｉの信頼性を損ねるのコンタクト穴領域
を除（、全面（上、下、側面）が熱酸化膜で覆われてい
る。特に、Ｏ２，Ｍ。[Problem to be solved by the invention] However, 0MO3 which is finer than submicron
In semiconductor devices, there is no margin for noise current that causes latch-up (except for the contact hole area, which impairs the reliability of LSI), and the entire surface (top, bottom, and side surfaces) is covered with a thermal oxide film.In particular, O2 ,M.
Ｚ 、ＦＺＳ ｉ基板の熱酸化膜ＳｉＯ２で覆われる時
は、Ｓ１基板と８１０２の安定した界面を持つので、界
面または表面リークを最小限に抑制でき、？高信頼性半
導体装置を得る。When the Z, FZSi substrate is covered with the thermal oxide film SiO2, it has a stable interface between the S1 substrate and the 8102, so interface or surface leakage can be suppressed to a minimum. Obtain a highly reliable semiconductor device.
本発明は、かがる従来の不具合を回避し、ラッチアップ
の生じない高信頼性な高集積ＣＭＯＳ半導体装置を提供
することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to avoid such conventional problems and provide a highly reliable, highly integrated CMOS semiconductor device that does not cause latch-up.
［課題を解決するための手段］
本発明によれば、０Ｍ０ＳＦＥＴからなる半導体装置に
おいて、ｎ型Ｍ ＯＳ Ｆ Ｅ Ｔ領域、及び、Ｐ型Ｍ
Ｏ３ＦＥＴ領域は、各々、下面及び側面のすべての領域
が絶縁膜で覆われている。このため、第６図に示すよう
な寄生バイポーラトランジスタＰ７ＬＰＴ２ 、ａＰｙ
ｂＴ、が存在せずランチアップが発生しない。また、Ｐ
型ＭＯ３ＦＥＴ領域とＮ型ＭＯＳＦＥＴ領域は、上面の
配線接続のため［実施例］
以下、実施例を用いて本発明を説明する。第１図は、本
発明によるＣＭＯＳ半導体装置の断面図である。Ｓｉ基
板１には、絶縁膜２で覆われて、ゲート電極１０．ゲー
ト膜９．ル１拡散層ソースドレイン８からなるＮチャン
ネルＭＯ８ＦＢＴがＰウェル５の中に形成され、同様に
、Ｐ＋拡散層ソースドレイン７を持つＰチャンネルＭＯ
３Ｆ’ＥＴｌ：Ｊ″−ルウエル６に形成されている。ル
ウエル乙には、ル１領域４．Ｐウェル５には、Ｐ十領域
３が存在し、各々のウェルの電位安定を保っている。[Means for Solving the Problems] According to the present invention, in a semiconductor device including a 0M0SFET, an n-type MOS FET region and a P-type M
The entire bottom and side surfaces of each O3FET region are covered with an insulating film. Therefore, parasitic bipolar transistors P7LPT2, aPy as shown in FIG.
bT does not exist and launch-up does not occur. Also, P
The MO3FET region and the N-type MOSFET region are used for wiring connection on the upper surface [Examples] The present invention will be described below using Examples. FIG. 1 is a cross-sectional view of a CMOS semiconductor device according to the present invention. The Si substrate 1 is covered with an insulating film 2 and has a gate electrode 10 . Gate film 9. An N-channel MO8FBT consisting of a well 1 diffused layer source drain 8 is formed in the P well 5, and similarly a P channel MO8FBT having a P+ diffused layer source drain 7 is formed in the P well 5.
3F'ETl:J'' - formed in the well 6.The well B has a L1 region 4, and the P well 5 has a P10 region 3, keeping the potential of each well stable.
本発明によれば、寄生バイポーラトランジスタが存在し
ない。このため、端子Ｂから雑音電流が入ってきても、
電源端子Ａから、接地端子Ｃに定常的な電流が流れるこ
とは無い。According to the invention, there are no parasitic bipolar transistors. Therefore, even if noise current comes in from terminal B,
No steady current flows from the power supply terminal A to the ground terminal C.
第２図〜第５図は、本発明による半導体装置の製猜工程
断面図である。以下、断面図のフローに従って本発明に
よる半導体装置の製造方法を説明する。ＯＺ、ＭＯＺ、
またはＦＺいずれかのＳ ｊ。2 to 5 are cross-sectional views of the manufacturing process of the semiconductor device according to the present invention. Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described according to a flowchart of cross-sectional diagrams. OZ, MOZ,
or FZ either S j.
基板１１．１４の２枚を熱酸化し、熱酸化ｊ換５１０２
１２．１ろを形成後、Ｓｉ基板１１と１４を接着させる
。この接着は、Ｓｉ基板１１と１４の表面を接触させｉ
ｏｏｏ℃以上の高温で熱処理することにより可能であ
る。次に、８１基板１４を裏面から研削し、適当な厚さ
（０１μｍ〜５７４７７１）のＳｉ／１ｉＮ４’を形成
する。すなわち８１基板１１上には、熱酸化ＳｉＯ□膜
１２，１３及び羊結晶Ｓｉ薄膜１４′が存在する。第２
図において、該Ｓ１薄膜１４′の素子分離領域は選択的
にＳｉ除去され、溝１５は下地の５ｉ０２１ｉ！１２゜
１６まで到達している。この後、熱酸化により５１０２
膜１６を形成する。Ｓｉ薄膜１４′は」二。The two substrates 11 and 14 are thermally oxidized, and thermal oxidation conversion 5102 is performed.
12. After forming the first layer, the Si substrates 11 and 14 are bonded. This adhesion brings the surfaces of the Si substrates 11 and 14 into contact with each other.
This is possible by heat treatment at a high temperature of ooo°C or higher. Next, the 81 substrate 14 is ground from the back side to form Si/1iN4' having an appropriate thickness (01 μm to 574,771 μm). That is, on the 81 substrate 11, there are thermally oxidized SiO□ films 12, 13 and a sheep crystal Si thin film 14'. Second
In the figure, Si is selectively removed from the element isolation region of the S1 thin film 14', and the groove 15 is formed in the underlying layer 5i021i! It has reached 12°16. After this, 5102 by thermal oxidation
A film 16 is formed. The Si thin film 14' is 2.
下１．側面すべての領域が熱酸化膜１２．１５または１
６で囲まれる。溝１５を絶縁膜１７で埋め込み、ゲート
電極１９．ゲート膜１８．及び、ゲート側避絶縁膜２０
を形成したのが第４図である。Bottom 1. Thermal oxide film 12.15 or 1 on all sides
Surrounded by 6. The groove 15 is filled with an insulating film 17, and the gate electrode 19. Gate film 18. And gate side insulation film 20
Figure 4 shows the formation of this.
ここで、Ｓｉ薄膜層１４’Ｐ、１４’ ルには、各々選
択的に不純物イオン注入することにより、Ｐ型Ｓｉ、Ｎ
型Ｓ１化可能である。第５図では、１４’Ｐ（７）ＩＰ
’ｒ）エルには、ゲート電極１９ 、 ｎ＋拡散層ソー
スドレイン２６を持っｎ１チャンネルＭＯＳＦＥＴが形
成され、１４’７Ｌのルウエルには、同様にＰ＋拡散層
を持つＰチャンネルＭ、 ＯＳ ＦＥＴが形成され、層
間絶縁膜２１に設けられたコンタクト穴を通して、ＡＬ
配装ｙｉ１２２が拡散層２３．２４と接続する。本発明
の製造方法によれば、ＰチャンネルＭＯＳＦＥＴ領域及
びＮチャンネルＭＯＳＦＥＴ領域は、各々、下面及び側
面のすべての部分、及び、配線接続のためのコンタクト
穴領域を除いた上面が、半導体基板１１または１４の熱
酸化ｊ漠で囲まれる。Here, by selectively implanting impurity ions into the Si thin film layers 14'P and 14', P-type Si, N-type
It can be made into type S1. In Figure 5, 14'P(7)IP
An n1 channel MOSFET having a gate electrode 19 and an n+ diffusion layer source/drain 26 is formed in the 'r) well, and a P channel MOSFET having a P+ diffusion layer is similarly formed in the 14'7L well. , through the contact hole provided in the interlayer insulating film 21,
Arrangement yi 122 connects with diffusion layer 23.24. According to the manufacturing method of the present invention, each of the P-channel MOSFET region and the N-channel MOSFET region has all parts of the lower surface and side surfaces, and the upper surface excluding the contact hole region for interconnection connected to the semiconductor substrate 11 or Surrounded by 14 thermal oxidation zones.
１発明の効果］
本発明の半導体装置及び製造方法は、上記で説明したよ
うに、寄生バイポーラトランジスターが存在せず、高集
積化してもラッチアップの不具合が生じない。また８１
基板（薄膜層１４′ ）と絶縁膜界面は、８１基板の熱
酸化膜５ｉｎ２／Ｓｉ界面からなり、界面や表面のリー
クが抑制できる。従って、本発明は、ラッチアップの生
じない高信頼性な高集積０Ｍ０８ＦＦｉＴからなる半導
体装置及びその製造方法を提供する。1. Effects of the Invention] As explained above, the semiconductor device and manufacturing method of the present invention do not have a parasitic bipolar transistor and do not cause latch-up problems even when highly integrated. Also 81
The interface between the substrate (thin film layer 14') and the insulating film is a thermal oxide film 5in2/Si interface of the 81 substrate, and leakage at the interface and surface can be suppressed. Therefore, the present invention provides a highly reliable semiconductor device made of a highly integrated 0M08FFiT that does not cause latch-up, and a method for manufacturing the same.
第１図は本発明による半導体装置の断面図。
第２図〜第５図は本発明による半導体製造方法の工程断
面図。
第６図は従来の半導体装置の断面図。
１．１１，１４．５１・・・・・・・・・半導体基板２
・・・・・・・・・絶縁膜
３・・・・・・・・・Ｐ 領域
４・・・・・・・・・ル１領域
５・・・・・・・・Ｐ−領域
３５・・・・・・ル 拡散層
３６・・・・・・ゲート電極
Ａ・・・・・・・・・電源端子
Ｂ・・・・・・・・・雑音流入端子
Ｏ・・・・・・・・・接地端子
ＲＩ ＃Ｒ２ＩＲ３、ｔｔ４・・・・・・基板抵抗以
上FIG. 1 is a sectional view of a semiconductor device according to the present invention. 2 to 5 are process cross-sectional views of the semiconductor manufacturing method according to the present invention. FIG. 6 is a sectional view of a conventional semiconductor device. 1.11, 14.51... Semiconductor substrate 2
......Insulating film 3...P region 4...Le1 region 5...P- region 35. Diffusion layer 36... Gate electrode A... Power supply terminal B... Noise inflow terminal O...・・Grounding terminal RI #R2IR3, tt4・・・・・・Board resistance or more
Claims (2)
、ｎ型ＭＯＳＦＥＴ領域、及び、Ｐ型ＭＯＳＦＥＴ領域
は、各々下面及び側面のすべての部分、及び、配線接続
のためのコンタクト穴領域を除いた上面が、絶縁膜で囲
まれてなることを特徴とする半導体装置。(1) In a semiconductor device consisting of complementary MOSFETs, the n-type MOSFET region and the p-type MOSFET region have all the lower and side surfaces, and the upper surface excluding the contact hole region for wiring connection. A semiconductor device characterized by being surrounded by an insulating film.
、ｎ型ＭＯＳＦＥＴ領域、及び、Ｐ型ＭＯＳＦＥＴ領域
は、各々、下面及び側面のすべての部分、及び配線接続
のためのコンタクト穴領域を除いた上面が、半導体基板
の熱酸化膜で囲まれることを特徴とする請求項１記載の
半導体装置の製造方法。(2) In a semiconductor device consisting of complementary MOSFETs, the n-type MOSFET region and the p-type MOSFET region each have all portions of the lower surface and side surfaces, and the upper surface excluding the contact hole region for wiring connection. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is surrounded by a thermally oxidized film of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1258205A JPH03120752A (en) | 1989-10-03 | 1989-10-03 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1258205A JPH03120752A (en) | 1989-10-03 | 1989-10-03 | Semiconductor device and its manufacturing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP37119199A Division JP3333485B2 (en) | 1989-10-03 | 1999-12-27 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03120752A true JPH03120752A (en) | 1991-05-22 |
Family
ID=17316972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1258205A Pending JPH03120752A (en) | 1989-10-03 | 1989-10-03 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03120752A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5804858A (en) * | 1995-06-08 | 1998-09-08 | Taiwan Semiconductor Manufacturing, Ltd. | Body contacted SOI MOSFET |
| US6689677B2 (en) | 1999-07-29 | 2004-02-10 | Stmicroelectronics, Inc. | CMOS circuit of GaAs/Ge on Si substrate |
-
1989
- 1989-10-03 JP JP1258205A patent/JPH03120752A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5804858A (en) * | 1995-06-08 | 1998-09-08 | Taiwan Semiconductor Manufacturing, Ltd. | Body contacted SOI MOSFET |
| US6689677B2 (en) | 1999-07-29 | 2004-02-10 | Stmicroelectronics, Inc. | CMOS circuit of GaAs/Ge on Si substrate |
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