JPH031228A - Floating point multiplier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a multiplication circuit for data in floating point format, and particularly to a floating point multiplication circuit according to the IEEE (Institute of Electronics Engineers) standard.

[Conventional technology]

FIG. 3 shows an example of the configuration of a conventional floating point multiplication device according to the IEEE standard, and FIGS. 4(A) and 4(B) show calculation flows for the exponent and mantissa parts. Operand Xe of the exponent part of the operand in the exponent part adder l
, Ye is performed (step St), and the mantissa multiplier 4 adds the operand Xs of the mantissa of the operand.
is multiplied by Ys (step #l), and when the multiplication result of the mantissa in this mantissa multiplier 4 overflows (step #2), an increment signal is sent to add +1 to the exponent. (Step S
3). Next, in order to express the addition result of the exponent part with bias, the bias subtracter 2 converts the exponent part into a bias value A.
is subtracted (step S4). Further, by inputting the increment signal to the selector 5, the multiplication result of the mantissa part from the mantissa multiplier 4 is softened to the right by one bit (step #3). Further, the rounding circuit 6 performs rounding processing on the result of multiplication of the mantissa part, and as a result, when the rounding circuit 6 outputs a rounding signal of +1 (step #4), the incrementer of the mantissa part 7, +1 is added to the multiplication result of the mantissa part from the selector 5 (step #5), and the calculation result Os of the mantissa part is output from the incrementer 7. Further, as a result of the +1 operation in the incrementer 7, a carry occurs, and when the incrementer 7 outputs an increment signal to the exponent part (step S5), in the incrementer 3 of the exponent part, +! for the addition result of the exponent part from bias subtractor 2! are added (step S6),
The calculation result Oe of the exponent part is output.

[Problem to be solved by the invention]

In floating point multiplication according to the IEEE standard, as described above, the exponent part is expressed with a bias, such as Xe-ASYe-A. A is the bias value, A=2 1
(n is the number of data hits). In this case, the addition result of the exponent part is (Xe-A) + (Ye-A) = (Xe
+Ye-A)-A, and the addition result of the exponent part is (Xe+
It is necessary to subtract Δ for a biased notation such as Ye-A), and a bias subtractor 2 is provided for this purpose. In addition to such calculations, an increment operation to the exponent part accompanying an overflow signal during multiplication of the mantissa part,
Two cases of increment operations are required, including an increment operation for the exponent part associated with rounding processing, and each increment operation is performed by the exponent part adder l and the incrementer 3. Therefore, assuming the case where the calculation time is the slowest, the rounding signal from the rounding circuit 6 enters the mantissa incrementer 7, and as a result of addition in this incrementer 7, a carry occurs, and the incrementer 7 When the increment signal is output, the increment operation is performed in the incrementer 3 and the exponent part calculation result Oe is output. In this case, the exponent part increment is output from the rounding signal output from the rounding circuit 6. Until an output result is obtained from -3, there will be a delay between the delay time in incrementer 7 for the mantissa part and the delay time in incrementer 3 for the exponent part. If the number to be handled is single precision, the incrementer 7 of the mantissa part is 24 bits, and the incrementer 3 of the exponent part is 8 bits, for a total of 32 bits, and for double precision, the incrementer 7 is 43 bits. , so that incrementer 3 is 11 bits and has a total width of 64 bits.
Since the bit width of each incrementer is very large, the delay time caused by these incrementers 7 and 3 is also large, which has the disadvantage that floating point multiplication time becomes long. or,
Regarding the calculation of the exponent part, there is a drawback that the circuit scale becomes large because an adder 1, a bias subtracter 2, and an incrementer 3 are required. The present invention has been made in view of the two drawbacks of the prior art, and it is an object of the present invention to provide a floating point multiplication device that shortens the multiplication time and has a simple circuit configuration.

[Means to solve the problem]

A floating point multiplication device according to the present invention is a floating point multiplication device that multiplies floating point format data.
A mantissa multiplier that multiplies s and Ys, and an exponent part Xe and Y
The subtraction manual section of the notation subtractor is equipped with an exponent adder that adds e, and a subtracter that subtracts the bias value A from the adder horn of the notation exponent adder. By inputting to the LSB an inverted signal of the logical sum of the increment signal outputted due to an overflow in the mantissa multiplier and the increment signal outputted due to the rounding process for the multiplication output of the mantissa multiplier. , the increment process in the exponent part is performed as (XeA)+(Ye−
A)-(Xe+Ye-A)-(A-1).

[Effect]

According to the above configuration, when an increment signal is output due to an overflow in the multiplication of the mantissa part, or a rounding signal of +I is output during rounding of the multiplication result, and as a result of a carry in the mantissa part, an increment signal is output. When the exponent part is incremented by inputting a predetermined signal to LSB of the subtraction input part of the subtracter, the exponent part is incremented.

【Example】

FIG. 1 is a control block diagram showing an embodiment of a floating point multiplication device of the present invention, and the same parts as in the conventional device of FIG. 3 are given the same reference numerals. The increment signal from the mantissa multiplier 4 is inputted to the selector 5 and inputted to the NOR circuit NOR.
The output signal of this NOR circuit NOH is input via the inverter INV to the least significant bit (LSB) of the subtraction Jγ input section of the bias subtractor 2 to which the bias value (A-1) is input. When the rounding signal from the rounding circuit 6 is input to the incrementer 7 of the mantissa part, the rounding signal is input to the AND circuit AND.
The m-bit signal from the selector 5 is also input to the AND circuit AND, and the output signal of this AND circuit AND is input to the other human power section of the NOR circuit NOR. Next, the operation of the multiplication device with the above configuration is shown in FIGS. 2(A) and 2.
This will be explained with reference to the calculation flow in Figure (B). When the mantissa multiplier 4 multiplies the mantissa parts Xs and Ys (step #11), the multiplication result overflows and an increment signal is output (step #12)
, the NOR circuit NOR outputs "the same" and sends it to the exponent part through the inverter INV to the LSH of the subtraction section of the bias subtractor 2.
0" is input manually. Therefore, in the bias subtracter 2,
(Xe+Ye-A) (A, -1), that is, (Xe+Ye
-A) - A to 1 is subtracted. On the other hand, when the increment signal is not output from the mantissa multiplier 4, "B" is manually input to the LSB of the subtraction input section of the bias subtracter 2, so in this bias subtracter 2, (Xe
+Ye-A)-((A-1)+1), that is, the same calculation (Xe+Ye-A)-A as described in the conventional example is performed. Therefore, when the increment signal is output from the mantissa multiplier 4, +1 is added to the addition output of the exponent part. The condition under which the exponent part is incremented by the increment signal from the mantissa multiplier 4 in this manner is hereinafter referred to as condition I. Also, by inputting this increment signal to the selector 5, the mantissa multiplication result from the mantissa multiplier 4 becomes 1.
Bits are shifted to the right (step #13). Next, the multiplication output from the mantissa multiplier 4 is rounded in the rounding circuit 6, and it is determined whether or not a rounded signal of +1 is output as a result (step #14). When is output, the incrementer 7 adds +1 to the mantissa multiplication value from the selector 5 (step #15), and the incrementer 7 outputs the mantissa multiplication result Os. Ru. In addition, in the mantissa part, it is determined whether the multiplication values of the m-bit mantissa part from the selector 5 are all "1" (step #16),
When all the valley bits of the notation multiplication value are "1", the addition of +1 in incrementer 7 causes a carry, and the exponent part needs to be incremented by 4. In this case, the AND circuit AND Then “B” is output and the NOR circuit NO.
By manually inputting R, the bias subtracter 2 increments the exponent part as described above. The condition in which the exponent part is incremented due to rounding as described above is hereinafter referred to as condition 2. In the case of condition 2, the signal from the AND circuit AND is used as the increment signal for the exponent part, and unlike the conventional device shown in FIG. can be shortened. On the other hand, the exponent parts Xe and Ye are added in the exponent part adder 2 (step Sl1), and then in the bias subtracter 2, the bias is subtracted from the addition result, but the mantissa part It is determined by the calculation whether condition 1 or condition 2 is satisfied (step S12). When condition 1 or condition 2 is satisfied, (Xe+Ye−
A) -A+1 is subtracted and an increment operation is performed on the addition result of the exponent part (step S
l3). On the other hand, if either condition 1 or condition 2 is not satisfied, (Xe+Ye-A)-A is subtracted (step 5I4), and no increment operation is performed on the exponent part. The bias subtracter 2 directly outputs the addition result of the exponent part. In addition, in the calculation flow of FIG. 2(B), Condition I and Condition 2 are
If the above holds true, there is a possibility that the exponent part will be incremented twice, but it will be explained below that in reality, both conditions 1 and 2 do not hold. Now, if we set the maximum value X5 = 2 -1 Ys = 2 -1 so that the multiplication of the mantissa operands Xs and Ys will cause an overflow, both of which have a width of m bits, then X5xYs-(2''-IO2''-1 ) 2m 2m+1 = 2-2 +1 -2"'(2m'-1)+1 Here, the term (2"'-1) indicates "m-1 pieces lined up, and 2m+1 The term is the previous term m+1
It shifts bits. That is, if both Xs and Ys are selected to have the maximum value, there are at most m-1 sequences of l, and even if the mantissa is added by +1 due to rounding, it will never be transmitted to the exponent. Because at this time, all m bits of the mantissa! This is because otherwise it will not be transmitted to the exponent part. Therefore, condition 1 and condition 2 can be received by the NOR circuit NOR which is a logical sum.

【Effect of the invention】

As explained above, in a floating point multiplier that multiplies data in floating point format, when a bias value is subtracted from the addition result of the exponent part, the LSB of the subtraction input section of the bias subtracter is , when an overflow signal is output from the mantissa multiplier, and when an increment operation is required for the exponent part due to rounding of the mantissa part, the bias subtracter calculates (Xe+Ye-A)-
By subtracting (A-1), the exponent part is +1
Since the increment is performed in the exponent part, an incrementer for incrementing, which was conventionally required for the exponent part, is no longer necessary, and the circuit can be simplified. In addition, since the logical product of the rounding signal from the rounding circuit and all the bits in the multiplication result of the mantissa part is used to determine whether or not an increment operation is to be performed on the exponent part due to the rounding process in the mantissa part, the conventional device As shown in the figure, it is no longer necessary to pass the rounding signal accompanying the rounding process through the incrementers 7 and 3 of the mantissa and exponent parts, and calculations can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a control block diagram showing an embodiment of a floating point multiplication device of the present invention, and FIGS. 2(A) and 2(B) are:
FIG. 3 is a control block diagram of a conventional floating-point multiplication device; FIG. 4(A) and FIG.
B) is a flowchart showing calculations in the exponent part and mantissa part in the multiplication device of FIG. 3; ■...Exponent adder, 2...Bias subtracter, 4...
・Mantissa multiplier, pupil... selector, 6... rounding circuit,
7...Incrementer-Nl't...Nor circuit, [
NV...inverter, AND...AND circuit.

Claims (2)

[Claims] (1) A floating-point multiplication device that multiplies floating-point format data, including a mantissa multiplier that multiplies mantissa parts Xs and Ys, an exponent adder that adds exponent parts Xe and Ye, and the exponent part Bias value A from the addition output from the adder
and an increment signal outputted due to an overflow in the mantissa multiplier to the LSB of the subtraction input section of the subtracter to which the bus value A is input, and a multiplication output of the mantissa multiplier. By inputting the inverted signal of the logical sum with the increment signal output during the rounding process, the increment process in the exponent part can be performed as (Xe-A)+(Ye-A)=(Xe+Ye-A)-
(A-1) A floating point multiplication device characterized by performing multiplication in the following format. (2) When determining whether or not an increment operation is to be performed on the exponent part due to the rounding process, the rounding signal from the rounding circuit,
2. The floating point multiplication device according to claim 1, which uses a signal of AND with all bits of the multiplication result of the mantissa part.