JPH03125437A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH03125437A JPH03125437A JP1263285A JP26328589A JPH03125437A JP H03125437 A JPH03125437 A JP H03125437A JP 1263285 A JP1263285 A JP 1263285A JP 26328589 A JP26328589 A JP 26328589A JP H03125437 A JPH03125437 A JP H03125437A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- gaas
- gate electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 69
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 23
- 150000001875 compounds Chemical class 0.000 claims abstract description 20
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 239000002344 surface layer Substances 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- 125000005842 heteroatom Chemical group 0.000 abstract description 2
- 239000007943 implant Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はヘテロ接合を持つ化合物半導体上に、異なるタ
イプのＦＥＴを並べて配置してなる半導体集積回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit in which FETs of different types are arranged side by side on a compound semiconductor having a heterojunction.
（ロ）従来技術
従来のこの種の半導体集積回路としては、例えば第３図
に示すものが知られている。ＩＥＥＥ Ｊｏｕｒｎａｌ
ｏｆ Ｑｕａｎｔｕｍ Ｅｌｅｃｔｒｏｎｉｃｓ、
Ｖｏｗ、 ＱＥ−２２，Ｎｏ、９”Ｒｅｃｅｎｔ Ａｄ
ｖａｎｃｅｓ ｉｎ Ｕｌｔｒａ−Ｈｉｇｈ−５ｐｅｅ
ｄ ＨＥＭＴ Ｔｅｃｈｎｏｌｏｇ３” Ｍａｓａｙｕ
ｋｉ ＡＢＥ、 ｅｔ ａｌ、（ＦｕｊｉＬｓｕ Ｌａ
ｂｏｒａｔｏｒｉｅｓ、 Ｌｔｄ、）参照。この半導体
集積回路は、半導体上に、ＤＣＦＬ （直結ＦＥＴロジ
ック）と呼ばれる回路を構成している。一つの半導体に
、異なるＨＥＭＴ、即ちＤタイプ（デイブレジョン型）
のＦＥＴとＥタイプ（エンハンスメント型）のＦＥＴと
を備えている。(b) Prior Art As a conventional semiconductor integrated circuit of this type, the one shown in FIG. 3, for example, is known. IEEE Journal
of Quantum Electronics,
Vow, QE-22, No, 9”Recent Ad
vances in Ultra-High-5pee
d HEMT Technology3” Masayu
ki ABE, et al, (FujiLsu La
boratories, Ltd.). This semiconductor integrated circuit includes a circuit called DCFL (direct-coupled FET logic) on a semiconductor. Different HEMTs in one semiconductor, i.e. D-type (day-breaching type)
FET and an E type (enhancement type) FET.
第３図において、３１はＧａＡｓ （化合物半導体）基
板、３２はこの基板りに備えたＧａＡｓ層、３３はこの
ＧａＡｓ層の上に形成されこのＧａＡｓ層とヘテロ接合
を形成するＡｌＧａＡｓ層、３３．３４．３５はＡＩＧ
ａＡｓ層３３上に順次積層してなるＧａＡｓ層、ＡｌＧ
ａＡｓ層、ＧａＡｓ層である。In FIG. 3, 31 is a GaAs (compound semiconductor) substrate, 32 is a GaAs layer provided on this substrate, 33 is an AlGaAs layer formed on this GaAs layer and forms a heterojunction with this GaAs layer, 33.34 .35 is AIG
A GaAs layer and an AlG layer are sequentially stacked on the aAs layer 33.
They are an aAs layer and a GaAs layer.
ＥタイプのＦＥＴ３６はＡｌＧａＡｓ層３３」二にゲー
ト電極３７を形成しており、一方Ｉ）タイプのＦＥＴ３
８はＡｌＧａＡｓ層３５上にゲート電極３９を形成して
いる５４０．４１、及びｌｌ ２はオーミック電極であ
り、４３．４４、及び４５はリードである。The E type FET 36 has a gate electrode 37 formed on the AlGaAs layer 33'', while the I) type FET 3
8 is a gate electrode 39 formed on the AlGaAs layer 35, 540.41, 112 is an ohmic electrode, and 43.44 and 45 are leads.
二の半導体集積回路はＥタイプのＦＥＴ３６と、Ｄタイ
プのＦＥＴ３８とを半導体」二に並べて配置しており、
両方のＦＥＴでＤＣＦＬを構成するようにしている。The second semiconductor integrated circuit has an E type FET 36 and a D type FET 38 arranged side by side in a semiconductor.
Both FETs constitute a DCFL.
（ハ）発明が解決しようとする課題
このような半導体集積回路は、ＤタイプのＦＥＴの活性
層がＥタイプのＦＥＴの活性層を含んでおり、両者の構
造を独立に設計、変更することが不可能であった。また
、ＥタイプのＦＥＴのゲート電極を形成する工程中に、
このゲート電極の堆積される半導体表面（ＡｌＧａＡｓ
層３３の表面）側にダメージを受ける恐れがあり、一方
これを避けるためには材料、工程に大きな制約を受ける
という欠点がある。(c) Problems to be Solved by the Invention In such a semiconductor integrated circuit, the active layer of the D-type FET includes the active layer of the E-type FET, and the structures of both cannot be designed and changed independently. It was impossible. Also, during the process of forming the gate electrode of the E type FET,
The semiconductor surface (AlGaAs) on which this gate electrode is deposited
There is a risk that the surface of the layer 33 may be damaged, and on the other hand, there are drawbacks in that there are significant restrictions on materials and processes in order to avoid this.
（ニ）課題を解決するための手段
本発明は、ヘテロ接合を持つ化合物半導体−Ｌに、Ｅタ
イプのＦＥＴとＤタイプのＦＥＴを並べて配置してなる
半導体集積回路において、前記各タイプのＦＥＴはそれ
ぞれのゲート電極が前記化＆物事導体の同一平面上に形
成されており、一方のタイプのＦＥＴには、そのゲート
電極直下の化合物半導体内に、前記ヘテロ接合に実質的
に達しない不純物イオンの注入領域が設けられているこ
とを特徴とするものである。そして、前記化合物半導体
は、化合物半絶縁性基板上に、表面付近に２次元電子ガ
ス層を持つＧａＡｓ層と、該ＧａＡｓ層とヘテロ接合を
形成する電子供給層を持つＡｌＧａＡｓ層と、該ＡｌＧ
ａＡｓ層の上部に形成されかつ表面に上記ゲート電極を
形成してなる表面層とを積層してなるものである。(d) Means for Solving the Problems The present invention provides a semiconductor integrated circuit in which an E-type FET and a D-type FET are arranged side by side on a compound semiconductor-L having a heterojunction, in which each of the above-mentioned types of FETs is Each gate electrode is formed on the same plane of the conductor, and one type of FET has impurity ions in the compound semiconductor directly below the gate electrode that do not substantially reach the heterojunction. It is characterized in that an injection region is provided. The compound semiconductor includes, on a compound semi-insulating substrate, a GaAs layer having a two-dimensional electron gas layer near the surface, an AlGaAs layer having an electron supply layer forming a heterojunction with the GaAs layer, and the AlG
A surface layer formed on the aAs layer and having the gate electrode formed on the surface thereof is laminated.
（ホ）作用
本発明においては、単一のヘテロ接合を持つ半導体の表
面から所定の深さにわたって選択的に不鈍物イオンを注
入し、そのイオン注入領域の有無で、異なるタイプのＦ
ＥＴを同一面上に設けるようにしているので、イオン注
入量を適当に選択することによって、一方のＦＥＴの特
性を他方のＦＥＴの特性とは独立に制御することができ
る。また、両方のＦＥＴのゲート電極を半導体の同一表
面上に形成することができ、そのためエピタキシャル成
長直後のウェハ上に、直接ゲート電極用の金属を堆積さ
せることができ、半導体及び金属両方の界面の劣化を防
止することができ、半導体集積回路の特性を向上させる
ことができる。(E) Effect In the present invention, inert ions are selectively implanted to a predetermined depth from the surface of a semiconductor having a single heterojunction, and different types of F
Since the ETs are provided on the same plane, the characteristics of one FET can be controlled independently of the characteristics of the other FET by appropriately selecting the amount of ion implantation. In addition, the gate electrodes of both FETs can be formed on the same surface of the semiconductor, which allows the metal for the gate electrode to be deposited directly on the wafer immediately after epitaxial growth, which degrades the interface between both the semiconductor and the metal. can be prevented, and the characteristics of the semiconductor integrated circuit can be improved.
（へ）実施例
本発明を実施例に基すき詳細に説明する。第１図は、本
発明の半導体集積回路の一例を示す概略構成図である。(f) Examples The present invention will be explained in detail based on examples. FIG. 1 is a schematic configuration diagram showing an example of a semiconductor integrated circuit of the present invention.
１は化合物半導体、２．３はこの化合物半導体内に形成
してなるデート電極、４．５、及び６はオーミック電極
である。1 is a compound semiconductor, 2.3 is a date electrode formed in this compound semiconductor, and 4.5 and 6 are ohmic electrodes.
第２図はこの半導体集積回路の製造方法の一例を示して
いる。第２図イは化合物半導体に金属（Ｗ）を堆積した
直後の半導体ウェハの断面図を示し、第２図口はイオン
打ち込み工程を示し、第２図ハは電極形成工程を示して
いる。FIG. 2 shows an example of a method for manufacturing this semiconductor integrated circuit. FIG. 2A shows a cross-sectional view of a semiconductor wafer immediately after metal (W) is deposited on a compound semiconductor, the opening in FIG. 2 shows an ion implantation process, and FIG. 2C shows an electrode forming process.
化合物半導体１は、半絶縁性を有するＧａＡｓよりなる
半絶縁性基板７と、この基板７上にＭＢＥ法により順次
成長させている１−ＧａＡｓ層（厚さ、０．６μｍ＞
８と、１−ＡｌＧａＡｓ層（厚さ、０．００２＃ｍ ）
９と、ｎ−ＡｌＧａＡｓ層（厚さ、０．０５Ｈ＋ｍ
： Ｓｉドープ、ｌＸｌ０” ｃｍ”）１０と、ｎ−Ｇ
ａＡｓ層（厚さ、０． Ｏｂ＋ｍ） １１とを備えてい
る。The compound semiconductor 1 includes a semi-insulating substrate 7 made of GaAs having semi-insulating properties, and a 1-GaAs layer (thickness, 0.6 μm>
8 and 1-AlGaAs layer (thickness, 0.002#m)
9 and n-AlGaAs layer (thickness, 0.05H+m
: Si-doped, lXl0"cm")10 and n-G
aAs layer (thickness, 0.Ob+m) 11.
化合物半導体１には、上記各層を成長させた後、すぐに
ゲート電極となるタングステン層１３が厚さ０．２μｍ
堆積される（第２図イ参照）。このとき、ＡｌＧａＡｓ
層１０はＷとＧａＡｓのショットキ接合の影響を受けて
完全に空乏化している。従って、この活性層はＥタイプ
である。一方、ＤタイプのＦＥＴを形成するため、不純
物イオン２８Ｓ１＋を注入してなる注入領域１２がＡｌ
ＧａＡｓ層１０内部に設けられている。このイオンは実
質的にＧａＡｓ層８に達しないように打ち込みのエネル
ギーが選ばれている。例えば、このイオンを打ち込む部
分のＷをＳ Ｆ ｈプラズマエツチングにより除去した
後、Ｌ記イオンを１０ｋｅＶで注入する。この注入では
、ドーズ量のピークは半導体ウェハ表面からの深さ０、
０２５μｍ程度であり、Ｇａ、Ａｓ層８のヘテロ界面側
にある２次元電子ガス層には到達しない。このイオン打
ち込みのため、第２図口に示すように、Ｗ層］３の上に
ホトレジスト層１４を形成し、この層】・１及びＷ層１
３の両方に開孔１５を設けるようにしている。The compound semiconductor 1 has a tungsten layer 13 with a thickness of 0.2 μm that will become a gate electrode immediately after growing each of the above layers.
(See Figure 2 A). At this time, AlGaAs
Layer 10 is completely depleted under the influence of the Schottky junction of W and GaAs. Therefore, this active layer is of E type. On the other hand, in order to form a D-type FET, the implanted region 12 formed by implanting impurity ions 28S1+ is Al.
It is provided inside the GaAs layer 10. The implantation energy is selected so that these ions do not substantially reach the GaAs layer 8. For example, after removing the W in the ion implantation portion by S F h plasma etching, the L ions are implanted at 10 keV. In this implantation, the dose peaks at a depth of 0 from the semiconductor wafer surface.
025 μm, and does not reach the two-dimensional electron gas layer on the hetero interface side of the Ga, As layer 8. For this ion implantation, a photoresist layer 14 is formed on the W layer ]3 as shown in the opening of FIG.
Opening holes 15 are provided in both of the holes 3 and 3.
このイオン打ち込みの終了後、ホトレジスト層１４を除
去し、ウェハ全面に再びタングステン層１６を０．２ｐ
ｍ堆積し、更に８５０℃５秒の赤外線アニールを施した
後、所定のゲート電極２．３を加工成形している。この
ゲート電極２．３を成形した後の半導体ウェハの表面に
、オーミック電極４．５、及び６を加−Ｌ成形する（第
２図ハ参照）。After completing this ion implantation, the photoresist layer 14 is removed, and a tungsten layer 16 of 0.2p is again applied to the entire surface of the wafer.
After depositing m and further infrared annealing at 850° C. for 5 seconds, a predetermined gate electrode 2.3 is formed. After forming the gate electrode 2.3, ohmic electrodes 4.5 and 6 are formed by L-forming on the surface of the semiconductor wafer (see FIG. 2C).
第４図は本発明の他の実施例を示すものである。これは
、２次元電子ガス層２１が電子供給層２２ （ｎ”Ａｌ
ＧａＡｓ層）のＬ側（半導体ウェハの表面側）に位置す
るいわゆる逆ＨＥＭＴ構造であることを特徴とするもの
である。この第４図中、第１図と同一符号は実質的に同
一の機能要素を示している。なお、２３は半絶縁層７上
に形成されている１−ＡｌＧａＡｓ層、２４は１−Ａｌ
ＧａＡｓ層、２５はｎ−ＩｎＧａＡｓ層である。FIG. 4 shows another embodiment of the invention. This is because the two-dimensional electron gas layer 21 is the electron supply layer 22 (n”Al
It is characterized by a so-called inverted HEMT structure located on the L side (front side of the semiconductor wafer) of the GaAs layer. In FIG. 4, the same reference numerals as in FIG. 1 indicate substantially the same functional elements. Note that 23 is a 1-AlGaAs layer formed on the semi-insulating layer 7, and 24 is a 1-AlGaAs layer formed on the semi-insulating layer 7.
The GaAs layer 25 is an n-InGaAs layer.
（ト）発明の効果
本発明は、以上の説明から明らかな如く、一つの化合物
半導体の上に異なるタイプのＦＥＴを並べて配置し、一
方のＦＥＴの特性を他方のＦＥＴの特性を変えることな
く、即ち独立的に変えることができるので、設計の自由
度を大きくすることができる。また、これらＦＥＴの各
ゲートは上記化合物半導体の同一平面上になるように形
成されているので、半導体表面をゲート金属ですぐに保
護することができ、両名の界面の劣化を防止することも
できる。(g) Effects of the Invention As is clear from the above description, the present invention provides for arranging different types of FETs side by side on one compound semiconductor, and changing the characteristics of one FET without changing the characteristics of the other FET. That is, since they can be changed independently, the degree of freedom in design can be increased. In addition, since each gate of these FETs is formed on the same plane of the compound semiconductor, the semiconductor surface can be immediately protected with gate metal, and deterioration of the interface between the two can be prevented. can.
第１図は、本発明の半導体集積回路の一例を示す概略構
成図である。第２図はこの半導体集積口路の製造方法の
一例の工程図（第２図イル第２図ハ）を示している。第
３図は従来の半導体集積回路の一例を示す構成図である
。第４図は本発明の他の実施例を示す構成図である。FIG. 1 is a schematic configuration diagram showing an example of a semiconductor integrated circuit of the present invention. FIG. 2 shows a process diagram (FIG. 2I) and FIG. 2C (FIG. 2C) of an example of a method for manufacturing this semiconductor integrated circuit. FIG. 3 is a configuration diagram showing an example of a conventional semiconductor integrated circuit. FIG. 4 is a block diagram showing another embodiment of the present invention.
Claims (2)
ＦＥＴとＤタイプのＦＥＴを並べて配置してなる半導体
集積回路において、前記各タイプのＦＥＴはそれぞれの
ゲート電極が前記化合物半導体の同一平面上に形成され
ており、一方のタイプのＦＥＴには、そのゲート電極直
下の化合物半導体内に、前記ヘテロ接合に実質的に達し
ない不純物イオンの注入領域が設けられていることを特
徴とする半導体集積回路。(1) In a semiconductor integrated circuit in which an E-type FET and a D-type FET are arranged side by side on a compound semiconductor awaiting a heterojunction, each type of FET has its gate electrode on the same plane of the compound semiconductor. One type of FET is provided with an impurity ion implantation region that does not substantially reach the heterojunction in the compound semiconductor directly under the gate electrode. circuit.
表面付近に２次元電子ガス層を持つＧａＡｓ層と、該Ｇ
ａＡｓ層とヘテロ接合を形成する電子供給層を持つＡ１
ＧａＡｓ層と、該ＡｌＧａＡｓ層の上部に形成されかつ
表面に上記ゲート電極を形成してなる表面層とを積層し
てなるものである特許請求の範囲第１項記載の半導体集
積回路。(2) The compound semiconductor is placed on a compound semi-insulating substrate,
A GaAs layer with a two-dimensional electron gas layer near the surface, and the G
A1 with an electron supply layer forming a heterojunction with the aAs layer
2. The semiconductor integrated circuit according to claim 1, comprising a stack of a GaAs layer and a surface layer formed on the top of the AlGaAs layer and having the gate electrode formed on the surface thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1263285A JPH03125437A (en) | 1989-10-09 | 1989-10-09 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1263285A JPH03125437A (en) | 1989-10-09 | 1989-10-09 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03125437A true JPH03125437A (en) | 1991-05-28 |
Family
ID=17387344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1263285A Pending JPH03125437A (en) | 1989-10-09 | 1989-10-09 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03125437A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001210657A (en) * | 2000-01-25 | 2001-08-03 | Furukawa Electric Co Ltd:The | Semiconductor device and method of manufacturing the same |
| JP2007275336A (en) * | 2006-04-07 | 2007-10-25 | Shiroki Corp | Seat |
| JP2012104801A (en) * | 2010-11-12 | 2012-05-31 | Jiaotong Univ | METHOD OF MANUFACTURING GaN-BASED THIN FILM TRANSISTOR |
-
1989
- 1989-10-09 JP JP1263285A patent/JPH03125437A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001210657A (en) * | 2000-01-25 | 2001-08-03 | Furukawa Electric Co Ltd:The | Semiconductor device and method of manufacturing the same |
| JP2007275336A (en) * | 2006-04-07 | 2007-10-25 | Shiroki Corp | Seat |
| JP2012104801A (en) * | 2010-11-12 | 2012-05-31 | Jiaotong Univ | METHOD OF MANUFACTURING GaN-BASED THIN FILM TRANSISTOR |
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