JPH03126228A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress the decrease in breakdown strength of a semiconductor element by directly depositing an insulating film on the silicon in an N<-> epitaxial region by a CVD method, or by overlapping a thin thermal oxide film and an insulating film by a CVD method on N<-> epitaxial silicon. CONSTITUTION:Silane, SiH4, N2, O2 and the like are made to react at the tem perature of about 400 deg.C by using a CVD method in order to form a mask oxide film directly on the silicon in an N<-> epitaxial region 14, and a mask oxide film (CVD) 17 having the thickness of 0.2mum is deposited on the N<-> epitaxial surface. After a collector diffused region 16 is formed, a P-type base region 21 is formed. A hole is partially opened in the mask oxide film 17 on an emitter forming region. Thereafter polycrystalline silicon 22 is grown. The polycrystal silicon 22 which is to become an emitter electrode is patterned. Then, an insulat ing film 20 such as a CVD oxide film is deposited. Thereafter, a base contact 26, a collector contact 18 and an emitter contact 23 are opened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of forming an insulating film on a silicon surface provided with a diffusion region.

[Conventional technology]

FIG. 4 shows an example of a conventional semiconductor integrated circuit device and its manufacturing method. In FIG. 4, a bipolar transistor section is shown as a semiconductor integrated circuit device.

As shown in FIG. 4(a), an element isolation region 12 is provided on the main surface of the semiconductor substrate, and a first layer wiring 25 for taking out from each region of the base, emitter, and collector is provided in the element isolation defined by this region. is provided. These first wirings 25 are connected to each diffusion region through contact holes formed in an insulating film provided on the main surface of the substrate.

Next, the manufacturing method will be explained with reference to FIG. 4(b). N+ buried region 13 and 1 on P-type silicon substrate ll.
An N-epitaxial region 14 is formed with a thickness varying in μm.

Next, selective etching of silicon is performed from the surface so as to reach the P-type silicon substrate 11, and a separation groove having a width of about 5 μm is formed. Next, ion implantation of boron or the like is performed to form a P+ inversion prevention region 15. Thereafter, an oxide-based insulating film is deposited and etched back so as to remain only in the isolation trenches, thereby forming element isolation regions 12.

Next, the surface of the N-epitaxial region 14 was oxidized by a thermal oxidation method in an oxidizing atmosphere at a temperature of about 100°C to form a 0.2 μm thick
A thick mask oxide film 17 is formed. Next, after forming the collector diffusion region 16, poron ions are implanted to form the P-type base region 21.

After opening the mask oxide film 17 on the N+ emitter region I9, the polycrystalline silicon 22 is grown, ions of arsenic or phosphorus are implanted, and the polycrystalline silicon 22 that will become the electrode is patterned. .A base contact 26 is formed by depositing an insulating film 2o such as a CVD oxide film with a thickness of 2 μm.
．． The collector contact 18 and emitter contact 23 are opened. Next, 300 people thickly put platinum, etc., and heat-treated (sintered) in a N2 atmosphere at 500°C to selectively expose Si to the base contact 26° collector contact ≠ hairline emitter contact 23 with platinum silicide. (Pt-8i)27 is formed. Next, a barrier metal 24 such as titanium tungsten (TiW) is sputtered and patterned, and then aluminum or the like is sputtered to form a first layer wiring 25. Through the above steps, the semiconductor integrated circuit device shown in FIG. 4(b) is completed.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit device manufacturing method described above, N-
The mask oxide film on silicon in the epitaxial region is 1
Since it is formed by a reaction between silicon and oxygen in a high-temperature oxygen atmosphere of approximately 000°C, approximately 0.1 μm is etched from the silicon surface of the N- epitaxial region, and the N+ buried region 13 is etched away by high-temperature heat treatment during oxidation. Since it rises into the upper epitaxial region, the effective thickness of the N-epitaxial region 14 is further reduced. As a result, contact between the P type base region 21 and the N+ buried region 13,
There is a problem in that the base-collector breakdown voltage (BVceo) decreases due to the proximity, and the manufacturing yield of transistors decreases accordingly.

An object of the present invention is to form a high-quality insulating film on an epitaxial region without performing high-temperature heat treatment. The device manufacturing method is a manufacturing method in which an insulating film is formed directly on a silicon substrate formed by forming a high concentration buried region and an epitaxial region on a semiconductor substrate, and the insulating film is formed by at least chemical vapor deposition (CVD).
D) It is included by law.

In detail, after introducing high concentration impurities of the opposite conductivity type into the main surface of a semiconductor substrate of one conductivity type, a process of forming a low concentration epitaxial region of the opposite conductivity type on the substrate, and a step of forming at least one conductivity type impurity in this epitaxial region. a step of forming a first insulating film by chemical vapor deposition directly above the epitaxial region; and a step of forming an opening in a predetermined region of the first insulating film to form a diffusion region in the epitaxial region. A step of providing an extraction electrode connected to the region, a step of forming a second insulating film on the entire surface, and a step of providing an opening in at least a predetermined region of the second insulating film to form a wiring in a predetermined shape. Contains. With this manufacturing method, when the first insulating film is formed, the epitaxial region is not eaten away from the surface and the high concentration buried region does not rise, so that the effective thickness can be maintained. Moreover, the effect can be further enhanced by using a low-temperature growth method such as DCVD when forming the second insulating film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a plan pattern diagram of a bipolar transistor section showing a first embodiment of the present invention, and FIG.
FIG. 2 is a cross-sectional view taken along the line AA' of the first embodiment shown in FIG. Regarding FIG. 1(a), the appearance shown in FIG. 4(a) is similar to the conventional example.
Since this is the same as a), the explanation will be omitted.

Next, the manufacturing method will be explained with reference to FIG. 1(b). N+ buried region 13 and 1μ on P type silicon substrate ll
An N-epitaxial region 14 is formed by changing the thickness by m. Next, the silicon is selectively etched from the surface to a thickness of about 5 μm, reaching the P-type silicon substrate 11. Next, ion implantation of boron or the like is performed to form a P+ inversion prevention region 15.

Thereafter, an oxide-based insulating film is deposited, and an etch-back process is performed to planarize it and form an element isolation region 12. Then N
- Silane SiHI, N2 at a temperature of about 400° C. using CVD method to form a mask oxide film directly on the silicon of the epitaxial region 14;

0□ etc. to form a 0.2 μm layer on the N-epitaxial surface.
Thick oxidation v! , 17 are deposited. Next, after forming the collector diffusion region 16, boron ions are implanted to form the P-type base region 21. Next, after partially opening the mask oxide film 17 on the emitter formation region, the polycrystalline silicon 2
2, and implanting ions such as arsenic or phosphorus,
Thereafter, the polycrystalline silicon 22 that will become the emitter electrode is patterned.

Next, after depositing an insulating film 2o such as a CVD oxide film with a thickness of 0.2 μm, the base contact 26. Collector contact 18 and emitter contact 23 are opened. Next, sputter platinum etc. to a different thickness by about 300 people and heat it at 500℃.
Heat treatment is performed in a N2 atmosphere to form platinum silicide (Pt-S
i) form 27; Next, apply barrier metal such as TiW to 0.
．． Sputter and pattern with a thickness of 1 μm,
Thereafter, aluminum is sputtered to a thickness of about 1 μm to form the first layer wiring 25.

Through the above steps, the semiconductor integrated circuit device shown in FIG. 1(, b) is completed.

FIG. 2 is a sectional view showing a second embodiment of the invention. In this example, the mask oxide film 17 using only the oxide film formed by the CVD method in the first example is grown on the oxide film 17-1 formed by the CVD method using plasma the size of several hundred holes. An oxide film, a nitride film, a nitride film formed by a reduced pressure method, or the like can be used. In particular, when a nitride film is used, it also has the effect of so-called gettering, which traps mobile ions and the like.

FIG. 3 is a sectional view showing a third embodiment of the present invention. In this embodiment, an oxide film 17 with a thickness of 0.15 μm is formed by CVD method.
A thin thermal oxide film 28 with a thickness of about 0.05 μm (500 people) is formed on the lower layer. In this structure, the formation of a thin thermal oxide film 28 shortens the high-temperature heat treatment time compared to the conventional one, so that the surface of the epitaxial region 14 is not eaten away.
The rise of the buried region 13 can be suppressed to a small level.

Although the present embodiment has been described above using a bipolar transistor, the present invention is not limited to this.
It goes without saying that similar effects can be obtained with diffused resistance and the like.

〔Effect of the invention〕

As explained above, in the present invention, a thin thermal oxide film is deposited directly on the silicon in the N-epitaxial region by the CVD method, or a thin thermal oxide film is superimposed on the N-epitaxial silicon by the CVD method to form an insulating film. The surface of the N-epitaxial region is hardly eaten away by the thermal oxide film, and the underlying buried region does not rise, reducing the factors that reduce the effective thickness of the N-epitaxial region compared to conventional methods. Therefore, the base-collector breakdown voltage (BVcao) can be improved, which has the effect of improving the manufacturing yield.

26...Base contact, 27...
Platinum silicon → J. Ido (Pt-8i), 28...
Thermal oxide film.

[Brief explanation of the drawing]

FIG. 1(a) is a plan pattern diagram of a bipolar transistor section showing a first embodiment of the present invention, and FIG.
2 is a cross-sectional view showing the second embodiment of the present invention; FIG. 3 is a cross-sectional view showing the third embodiment of the present invention; FIG. 4(a) is a plan pattern diagram of a bipolar transistor section showing a conventional example, and FIG. 4(b) is a sectional view taken along the line BB' of FIG. 4(a).

Claims (1)

[Claims] 1. After introducing high concentration impurities of the opposite conductivity type into the main surface of a semiconductor substrate of one conductivity type, growing a low concentration epitaxial region of the opposite conductivity type on the main surface of the substrate; forming a diffusion region of at least one conductivity type in the epitaxial region; forming a first insulating film by chemical vapor deposition directly above the epitaxial region; and forming a first insulating film in a predetermined region of the first insulating film. providing an opening and providing an electrode connected to the diffusion region in the epitaxial region;
A semiconductor comprising the steps of forming a second insulating film over the entire surface, and forming an opening in at least a predetermined region of the second insulating film to form a wiring having a predetermined shape. A method of manufacturing an integrated circuit device. 2. Claim 1, wherein the step of forming the first insulating film is a step of forming an insulating film by plasma growth on an insulating film formed by chemical vapor deposition. A method of manufacturing the semiconductor integrated circuit device described above. 3. The step of forming the first insulating film is a step of forming a thin thermal oxide film of about several hundred Å, and then forming an insulating film on the thermal oxide film by chemical vapor deposition. A method for manufacturing a semiconductor integrated circuit device according to claim 1.