JPS6489364A - Manufacture of bipolar semiconductor integrated circuit device - Google Patents

Manufacture of bipolar semiconductor integrated circuit device

Info

Publication number
JPS6489364A
JPS6489364A JP62244741A JP24474187A JPS6489364A JP S6489364 A JPS6489364 A JP S6489364A JP 62244741 A JP62244741 A JP 62244741A JP 24474187 A JP24474187 A JP 24474187A JP S6489364 A JPS6489364 A JP S6489364A
Authority
JP
Japan
Prior art keywords
layer
type
collector
emitter
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62244741A
Other languages
Japanese (ja)
Other versions
JPH061785B2 (en
Inventor
Katsunori Tsuda
Shogo Kamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62244741A priority Critical patent/JPH061785B2/en
Publication of JPS6489364A publication Critical patent/JPS6489364A/en
Publication of JPH061785B2 publication Critical patent/JPH061785B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce the increasing amount of an area of an emitter electrode lead due to overetching by retaining an Si nitride film remaining on an emitter layer forming region so as to be superposed on a collector layer, and forming a collector electrode lead in the region of the film. CONSTITUTION:An N<+> type collector buried layer 2, an N-type epitaxial layer 3, a P<+> type isolation layer 4, an N<+> type collector layer 6 and an oxide film 5 are formed on a P<+> type semiconductor substrate 1. An Si nitride film 9 to be retained on a region for forming an N<+> type emitter layer 10 so remains as to be superposed on the layer 6. Then, a P<+> type external base layer 7 and a P<-> type active base layer 8 are formed. A hole for forming the layer 10 is opened by etching. An oxide film 501A on the N<+> type collector layer is reduced in thickness as compared with the oxide film 500B on the P<+> type external base layer. After the layer 10 is formed by ion implanting a CVD oxide film 11 is formed on a whole surface, and a resist 14 is patterned to form collector, emitter and base electrode leads 15A, 15, 15B.
JP62244741A 1987-09-29 1987-09-29 Method for manufacturing bipolar semiconductor integrated circuit device Expired - Lifetime JPH061785B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62244741A JPH061785B2 (en) 1987-09-29 1987-09-29 Method for manufacturing bipolar semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62244741A JPH061785B2 (en) 1987-09-29 1987-09-29 Method for manufacturing bipolar semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6489364A true JPS6489364A (en) 1989-04-03
JPH061785B2 JPH061785B2 (en) 1994-01-05

Family

ID=17123201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62244741A Expired - Lifetime JPH061785B2 (en) 1987-09-29 1987-09-29 Method for manufacturing bipolar semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH061785B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03126228A (en) * 1989-10-12 1991-05-29 Nec Corp Method for manufacturing semiconductor integrated circuit device
US10080999B2 (en) 2014-01-17 2018-09-25 Ttp Labtech Ltd. Sample vessel agitation apparatus and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021568A (en) * 1983-07-15 1985-02-02 Hitachi Ltd Manufacturing method of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021568A (en) * 1983-07-15 1985-02-02 Hitachi Ltd Manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03126228A (en) * 1989-10-12 1991-05-29 Nec Corp Method for manufacturing semiconductor integrated circuit device
US10080999B2 (en) 2014-01-17 2018-09-25 Ttp Labtech Ltd. Sample vessel agitation apparatus and method

Also Published As

Publication number Publication date
JPH061785B2 (en) 1994-01-05

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