JPH03127162A - How to access CPU shared memory - Google Patents

Abstract

PURPOSE:To shorten an access time by making an access instruction executed from that time invalid, changing forcibly the succeeding instruction to a jump instruction and re-executing the invalid access instruction, when the other CPU is executing an access to a shared memory, if one CPU executes an access to the shared memory. CONSTITUTION:A CPU 1 with a wait/hold function and a CPU 2 without a wait/hold function are contained, and when the CPU 2 executes an access to a shared memory 20, unless the CPU 1 is not executing an access to the shared memory 20, the access of the shared memory 20 can be executed. On the other hand, when the CPU 2 executes an access to the shared memory 20, if the CPU 1 executes an access already to the shared memory 20, a competition arbitrating circuit 10 turns on an access invalid signal 15. Also, an instruction sequence control circuit 11 executes an invalid access instruction to the shared memory 20, and thereafter, switched to a jump instruction generating circuit 13, and re-executes an access to the shared memory 20. In such a way, the time for executing an access to the shared memory can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an access method when a CPU without a wait/hold function accesses a shared memory in a shared memory multi-CPU system.

[Conventional technology]

A shared memory access method when using a conventional CPU without a wait/hold function will be explained based on FIGS. 5 and 6.

FIG. 5 is a block diagram of a conventional shared memory 20 and its peripheral circuits. In the figure, 1 is a CPU with a wait/hold function, and 2 is a CPU without a wait/hold function, both of which are configured to be able to access the shared memory 20 in common. 3^, 3B is the request flag, 4^,
4B is address buffer, 5^, 5B is data buffer, 6^, 6B is control gate, 7A, 7B
+*Indicates decoder.

61st! I is a flowchart of a program used when accessing the shared memory 20 installed in the CPUI with wait/hold function.

Regarding the program installed in CPU2 without wait/hold function, CPU1°CPU2 is also removed in Figure 6.
LzotLCPU2. This can be realized by replacing the CPUI.

In the conventional example, when either CPU accesses the shared memory 20, the other CPU has already accessed the shared memory 20.
Check request flags 3A and 3B to see if they are being used, and if not, set request flag 3A3B to declare that the shared memory 20 will be used by the other CPU. If so, wait until it is finished using.

Next, at the same time as request flags 3A and 3B are set, the other CPU checks whether the request flags 3^ and 3B are set. request flag 3A,
After clearing 3B and setting the contention timer, wait for timeout and check request flag 3^ and 3B again. The other CPU has the request flag 3A.

If 3B is not set, it is determined that no access is being made, and after accessing the shared memory 20, the request flag 3 is set.
By clearing 3B, the other CPU can access the shared memory 20.

[Problem to be solved by the invention]

In the conventional technology, even when accessing data in a shared memory of at most 1 byte, many programs as shown in FIG. 6 are required, so access takes time.

Furthermore, if the other CPU accesses the shared memory in block units (consisting of multiple bytes), the other CPU
The waiting time for waiting until the PU is finished being used increases, and as a result, access takes even more time.

Therefore, an object of the present invention is to shorten the access time.

[Means to solve the problem]

To achieve this object, the CPU shared memory access method of the present invention includes a CPU shared memory access method that does not have a wait/hold function.
When U attempts to access shared memory, the other CP
If U is not accessing the shared memory, it will continue to access it; if the other CPU is accessing the shared memory, it will invalidate the access instruction to be executed and force the subsequent instruction to jump. This feature is characterized in that an access command that has been invalidated is re-executed by changing it to .

[Effect]

By the above means, when a CPU without a wait/hold function attempts to access shared memory, no software is required to arbitrate the conflict, which simplifies the software and makes it easier to access shared memory. The time required for this is significantly reduced.

〔Example〕

Embodiments of the present invention will be specifically described below based on the embodiments shown in FIGS. 1 to 4.

FIG. 1 is a block diagram of a shared memory and its peripheral circuits according to the present invention, and includes a CPU 1 with a wait/hold function.
and a CPU2 without a wait/hold function. Note that elements having functions corresponding to those of the conventional example shown in FIG. 5 are designated by the same reference numerals, and description thereof will be omitted. In FIG. 1, 8 represents an address bus, and 9 represents a data bus.

When the contention arbitration circuit 10 in FIG. 1 receives an access request signal 15^ for the shared memory 20 from the CPU 1, it turns off the wait signal 16 if the other CPU 2 is not accessing the shared memory 20. Access is permitted, and if the other CPU2 is accessing, wait signal 1
6 is turned on, the execution of the access is kept waiting, and after the other CPU 2 completes the access operation, the wait signal 16 is turned off to permit access. On the other hand, from CPU2 to shared memory 20
When the access request signal 15B of the other CP is received, the other CP
If U1 is not accessing, the access invalidation signal 17 is turned off to execute the shared instruction access, and if the other CPUI is accessing, the access invalidation signal 17 is turned off.
It has the function of prohibiting access to the shared memory 20 by turning on the switch and requesting the instruction sequence control circuit 11 to change the instruction sequence.

If the access invalidation signal 17 is off, the instruction sequence control circuit 11 in FIG.
4 is input to the program memory, normal processing is executed. However, if the access invalidation signal 17 is on, the human power of the instruction source multiplexer 14 is transferred to the jump instruction generation circuit 13 after executing the access instruction currently being executed. By switching, it has the function of jumping to the access command again.

Next, the operation in the embodiment will be explained. When CPU2 attempts to access shared memory 20, CPU1
is not accessing the shared memory 20, the contention arbitration circuit 10 turns off the access invalidation signal 17.
Address buffer 4B and data buffer 5B of CPU2
The control gate 6B is opened and the shared memory 20 can be accessed.

Furthermore, since the access invalidation signal 17 is off, the instruction source multiplexer 14 also selects the program memory 12 and executes the program according to the normal sequence.

On the other hand, when the CPU 2 tries to access the shared memory 20, if the (:PUl) has already accessed the shared memory 20, the contention arbitration circuit 10 sends the access invalidation signal
is turned on, the address buffer 4, f-ta buffer 75B, and control gate 6B of the CPU 2 remain closed, and writing and reading to and from the shared memory 20 are not executed correctly and become invalid. Also, access invalid signal 1
7 is on, the instruction sequence control circuit 11 executes the invalid access instruction to the shared memory 20 and then jumps to the program memory address where the access instruction that invalidates the input of the instruction source multiplexer 14 is stored. By switching to the jump instruction generation circuit 13 in which the jump instruction is stored, access to the shared memory 20 is re-executed without software intervention.

This access to the shared memory 20 is re-executed by the shared memory 2
This is repeated until the access to 0 is performed normally, but
- Since cptri shared memory accesses are not executed continuously within the shell, the CPU 2 can access the shared memory 20 by re-executing the access once at most.

Regarding the shared memory access by the CPU 2, time charts are shown in FIGS. 2 and 3 for cases in which the access is normally completed once and when the access is normally completed by re-executing the access a plurality of times.

In addition, Fig. 4 shows C without a wait/hold function.
The instruction execution operation for transferring 1 byte from the shared memory to the internal memory when the Intel CPU 3051 is used as the PU is explained using a program list.

In FIG. 4, 30 represents an internal memory, 31 a shared memory, 32 a read command from the shared memory, 33 a forced jump command, and 34 a write command to the internal memory.

In this embodiment, a contention arbitration circuit 10 using a wait signal is employed, but a contention arbitration circuit using a hold signal is also possible.

Although CPU1 is described as having a wait function, it may also be a CPU without a wait function.In that case, by using the same circuit as CPU2, it is easy to connect CPUs without a wait function. Multi-CPU systems are possible.

〔Effect of the invention〕

As described above, according to the present invention, when a CPU that does not have a wait/hold function attempts to access shared memory, if the other CPU is accessing the shared memory, the access operation to be executed is executed. The software for arbitrating access conflicts is designed to repeat the access operation until the other CPU is no longer in use by invalidating it and forcibly changing the subsequent instruction to a jump instruction. There is no need for this at all, which has the effect of simplifying the software and shortening the time required to access the shared memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of hardware of the present invention,
Figures 2 and 3 are time charts of shared memory access according to the present invention, Figure 4 is an explanatory diagram of shared memory access re-execution using a program list, and Figure 5 is a diagram of conventional shared memory system hardware. The block diagram, FIG. 6, is a flowchart showing the software processing required in conventional Hatware. 1: CPU with wait/hold function 2: CPU without wait/hold function 3A, 3B: Request flag 4A, 48 nearest address buffer 5A, 5B: Data buffer 6^, 6B = control gate 7^, 7B: Decoder 8 nearest address Bus 9: Data path IO: Conflict arbitration circuit 11: Instruction sequence control circuit 12 Niprogram memory 13: Jump instruction generation circuit 14: Instruction source multiplexer 15^, 158: Access request signal 16 Two-wait signal 17: Access invalid signal 0 :shared memory

Claims (1)

[Claims] 1. In a shared memory access method for a CPU that does not have a wait/hold function, when the CPU attempts to access the shared memory, if the other CPU is not accessing the shared memory, the CPU continues to access the shared memory, The feature is that when the other CPU is accessing the shared memory, the access instruction to be executed from now on is invalidated, and the subsequent instruction is forcibly changed to a jump instruction, thereby causing the invalidated access instruction to be re-executed. How to access the shared memory of the CPU.