JPH0520212A - Control circuit using dual port RAM - Google Patents

Abstract

(57) [Abstract] [Purpose] To prevent malfunction by detecting an abnormality due to simultaneous access of DPRAM when a CPU without a wait function is connected to one side of DPRAM. [Structure] CP that does not have wait function from DPRAM
Upon receiving the BUSY signal output to U, this CP
An abnormality detection circuit 4 for outputting an error signal for prohibiting access of the DPRAM by U is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port RAM (hereinafter referred to as DP) capable of independently asynchronously reading and writing from any port of both sides to any address of the memory.
Control circuit using RAM).

[0002]

2. Description of the Related Art Generally, a control circuit (system) is constructed by connecting a CPU having a wait function to each port on both sides of a DPRAM.

Considering the operation when the same address of the memory is selected from two ports in such a control circuit, there is no problem when both ports are operating in the read mode, but one port writes. In the case of operating in the mode, the read data of the reverse port during the read operation may change in the middle due to writing.

Further, in the case of a write operation at both ports, there is a possibility that the contents of the memory may become indefinite by writing the opposite data to each other, and this also poses a problem.

From this background, the BUSY signal is sent from the BUSY (busy) terminal of the post-arrival port to the corresponding wait terminal of the CPU regardless of which mode the ports are operating in, the read or the write. Send,
Until the BUSY signal turns off, in other words DPRA
There has already been proposed a DPRAM that controls so that the access operation from the later-arriving CPU is prohibited until the access operation of the CPU accessing M is completed.

In this case, both CPUs have a wait terminal (port) so that the wait function can be achieved, so the above control is possible, but the versatility of the CPU is expanded depending on the circuit. Alternatively, in order to reduce the cost, one of them may be a CPU having no wait function.

[0007]

As described above, when one CPU is provided with the wait function and the other CPU is not provided with the wait function, the same address of the memory is selected from two ports and the wait function is provided. When the CPU that does not have the latter arrives later, the above-mentioned inconvenience occurs.

According to the present invention, when one of the CPUs connected to the two ports of the DPRAM has no wait function, an abnormality caused by simultaneous access to the DPRAM is detected to prevent malfunction. DP that can
It is an object to provide a control circuit that uses a RAM.

[0009]

In order to achieve the above object, the present invention provides a second CP having no weight function.
BUSY signal from DPRAM output to U, and first and second CPs accessing DPRAM
An error detection circuit for generating an error signal from the address latch signal from U and outputting the error signal to the second CPU to prohibit access by the second CPU is provided.

[0010]

The BUSY signal from the DPRAM is input to one of the AND gates (first negative logic input) forming the abnormality detection circuit.

On the other hand, an output terminal is connected to the other input terminal of the (first negative logic input) AND gate, and an output terminal is connected to each input terminal of the (second negative logic input / output) AND gate which constitutes an abnormality detection circuit. Receives the address latch signals of the first and second CPUs.

The output of the (first negative logic input) AND gate is input to the CK terminal of the D flip-flop forming the abnormality detection circuit, and the Q output outputs an error signal. When this error signal is taken in by the second CPU, the second CPU prohibits access to the DPRAM.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a DPRAM according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a control circuit that uses a CPU, where 1 is a first CPU having a wait function and 2 is a second CPU not having a wait function.
CPU 3 is DPRAM having ports on both sides connected to the ports of CPUs 1 and 2, and 4 is an abnormality detection circuit.

The abnormality detection circuit 4 includes a negative logic input / output AND gate 41, a negative logic input AND gate 42 to which an output terminal of the negative logic input / output AND gate 41 is connected to one input terminal, and this negative logic input. It is composed of a D flip-flop 43 whose output terminal is connected to the CK terminal, and a negative logic input / output OR gate 44 which sends out a signal for resetting and clearing the CLR terminal of the D flip-flop 43.

In FIG. 1, (1) to (12) are signals of respective parts, and FIG. 2 shows a timing chart thereof. Here, the same address of the DPRAM 3 is assigned to the first CPU 1 and the second CPU 2. If both are accessed and the second CPU 2 arrives later, DPRAM3
The BUSY signal (10) is originally output to the second CPU 2 from the BUSY terminal, but since the second CPU 2 does not have a wait terminal, the negative logic input AND gate of the abnormality detection circuit 4 is used in this embodiment. It is input to the other input terminal of 42.

On the other hand, the address latch output (4) of the first CPU 1 and the address latch output (9) of the second CPU 2
ANDed with the negative logic input / output AND gate 41,
This output is input to one input terminal of the negative logic input AND gate 42.

The output signal (11) resulting from the logical product of the two is as shown in (11) of FIG. 2, and when this is input to the CK terminal of the D flip-flop 43, an error signal (12) is output from the Q output. And is taken into the second CPU 2.

The second CPU 2 receives this error signal (1
2), access to the DPRAM3 is prohibited,
Further, the access becomes possible only after the BUSY signal (10) is turned off.

[0020]

As described above, according to the present invention,
Even when a CPU having no wait function is connected to one port of DPRAM, it receives a BUSY signal to this CPU to detect an abnormality, and DPRA by this CPU
Since an abnormality detection circuit that prohibits M access is provided, D
It is possible to prevent a trouble (a trouble that the read data changes in the middle or a trouble that the content of the write data becomes indefinite) that occurs when the PRAMs are simultaneously accessed, and perform control without malfunction.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a control circuit using a DPRAM according to an embodiment of the present invention.

FIG. 2 is a timing chart of signal waveforms at various parts of the circuit shown in FIG.

[Explanation of symbols]

1st CPU 2 Second CPU 3 DPRAM 4 Abnormality detection circuit 41 Negative logic input / output AND gate 42 Negative logic input AND gate 43 D flip-flop

Claims (2)

[Claims] 1. A control circuit in which a first CPU having a wait function is connected to one port of a dual port RAM and a second CPU having no wait function is connected to the other port of the dual CPU, wherein the first CPU is provided. When the dual port RAM is accessed from one port via one port, the busy signal output from the other port and the first and second CPUs
Of the address latch signal output from the address latch port terminal of the CPU, generates an error signal, outputs the error signal to the second CPU, and prohibits the access of the dual port RAM by the second CPU. A control circuit using a dual port RAM, which is provided. 2. The control circuit using a dual port RAM according to claim 1, wherein the abnormality detection circuit is composed of a plurality of logic gates and flip-flops.