JPH0312733A - Storage device - Google Patents

Abstract

PURPOSE:To prevent the unsteady state of a fraction part of the input data by providing an output data latch part, an output data switch part, and an output switching signal generating part. CONSTITUTION:The fractions '9' and '10' of the input data 301 are not written into a storage part 33. A read signal 306 is inputted to an output switching signal generating part 13 to acquire a switching signal 102 which is set at H levels at three output points. Then the output of an output data shift register 35 is held by an output data latch part 11 at a rise point. The signal 102 is applied to an output data switching part 12, and the output of the register 35 is defined as the output data 101 when the signal 102 is kept at an L level. Simultaneously, the output of the part 11 is defined as the data 101 when the signal 102 is kept at an H level. Thus the part 11 is controlled by the signal 102 of the part 13 and the part 11 holds the data 1 - 8 obtained right before a traction part outputted from the register 35. Similarly, the signal 102 is used as a control signal and the data 101 is defined as the output of the register 35 by the part 12 at a time point preceding by an extent equal to the fraction part. The output of the part 11 is secured at the fraction part. Consequently, an unsteady state is never produced at the fraction part of the output data.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides a serial/parallel conversion circuit (hereinafter referred to as S/
The present invention relates to a storage device using a P-conversion circuit (abbreviated as P-conversion circuit).

2. Description of the Related Art In recent years, as video signals have been digitally processed, storage devices have come to be used in video equipment such as television receivers and video cameras.

In order to record video signals in a storage device, it is necessary to digitize them. For example, in NTSC, when sampling is performed at a sampling frequency four times the color subcarrier frequency, the display time of one sampling point is approximately 70 ns. On the other hand, dynamic random access memory (DRAM) is a semiconductor memory device.
), the operations include writing, reading, and rewriting, and the time required for each operation is 200 minutes.
It is about ns. In other words, the operating speed of a semiconductor memory device is considerably slower than the display time of one sample point of a video signal. Therefore, in conventional semiconductor memory devices, S/P
By using a conversion circuit, the speed was adjusted by processing several sample points at once.

A conventional storage device will be explained below. FIG. 3 is a block diagram of a conventional memory device formed on a semiconductor chip, in which 31 is an input data shift register unit that converts data 301 that is continuously input in series into parallel data;
Reference numeral 2 denotes an input data storage register section for temporarily storing the output from the input data shift register section 31 before writing it into the storage section 33; and 34, a register section for temporarily storing the data read out from the storage section 33. 35 is an output data shift register section that stores output data and stores it when output data is stored. 35 is an output data shift register section that converts parallel data output from the register section 34 into serial output data 303. 36 is an input reference. A write signal generation section 37 counts the clock 302 and generates a write signal 305, and a read signal generation section 37 counts the output reference clock 304 and generates a read signal 307.

Next, the operation of this storage device will be described with reference to the timing diagram of FIG. 4, taking as an example the case where the number of S/P conversion stages is four. First, the write operation will be explained. Input data 301 and input reference clock 302 are input to input data shift register section 31 . Here, the input data 301 is input to the shift register at a rate of one data per one clock, as shown in FIG. 4(a). At the same time, an input reference clock 302 is inputted to the write signal generating section 36 and counted by a counter, thereby obtaining a write signal 305 which becomes high state once every four clocks. This write signal 305
is stored as input data and inputted to the register section 32, and when the write signal 305 is in a high state, the data in the input data shift register section 31 is stored as input data and inputted to the register section 3.
Transfer to 2. Then, the data is stored as input data, transferred to the register section 32, and then written to the storage section 33. Next, the read operation will be explained. Data corresponding to the number of S/P stages is read out from the storage section 33, stored when it is output data, and held in the register section 34. At this time, by inputting the output reference clock 304 to the readout signal generating section 37 and counting it with a counter, the readout signal 306 shown in the timing diagram of FIG. 4(b) becomes high once every four clocks. get. When the read signal 306 is output data, it is stored and input to the register section 34, and the read signal 306 is stored as output data.
When 06 is in a high state, data is transferred to the output data shift register section 35. By inputting the output reference clock 304 to the output data shift register section 35, the output data 30 is output once every clock by the operation of the shift register.
Output 3 serially.

Problems to be Solved by the Invention However, in the above conventional configuration, when the number of input data is not a multiple of the number of S/P conversion stages and has a fractional part, the data of the fractional part is transferred to the input data shift register section. Since the write signal 305 for storing input data and transferring it to the register section 32 is not generated from the input data 31, the fractional data is not written to the storage section 33. Also,
Since no data has been input to the storage unit 33 at the time of reading, it is not known what kind of data will be output. For example, input data 3 of 10 pieces of data shown in FIG. 4(a)
When writing 01 to the storage unit 33, a write signal 305 is generated for each data from 1 to 8, so the storage unit 3
3, but the fractional portions of data 9 and 10 are not written to the storage unit 33 because the number of clocks of the input reference clock 302 is less than four, and the write signal 305 is not generated. Furthermore, when reading out the 10 output data 302 in FIG. The data of 9°10 that is not input and is read becomes undefined data.

The present invention solves the above-mentioned conventional problem, and even if there is a fractional part in the input data 301, when outputting, the data immediately before the fractional part is used as the data of the fractional part. An object of the present invention is to provide a storage device that can prevent data from becoming unstable.

Means for Solving the Problems To achieve this object, the storage device of the present invention includes an output data latch section that holds data immediately before the fractional part of the data output from the storage section; It includes an output data switching section for outputting the output of the data latch section as fractional data, and an output switching signal generation section for generating a switching signal for controlling the output data switching section.

Effect With this configuration, if the input data is not a multiple of the number of S/P conversion stages but has a fractional part, and the fractional part is not written to the storage unit, when reading, this fractional part is replaced with the data immediately before the same fractional part. By doing so, it is possible to prevent the data in the fractional part from being in an undefined state.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a memory device formed on a semiconductor chip in an embodiment of the present invention. Corresponding parts with the conventional example in Fig. 3 are given the same reference numerals and explanations are omitted.
Only the different parts will be explained. Further, as in the conventional example, the number of S/P conversion stages of the storage device is four. 11 is an output data latch section that holds the output of the output data shift register section 35 by a latch circuit; 12 is an output data switch that switches between the output of the output data shift register section 35 and the output of the output data latch section 11 and outputs the output data 101. Department,
Reference numeral 13 denotes an output switching signal generating section that outputs the output switching signal 102 by counting the read signal 306 with a counter.

The operation of the storage device configured as described above will be explained below. Further, here, explanation will be given taking as an example a case where ten data items numbered 1 to 10 shown in the timing diagram of FIG. 2 are used as input data 301.

First, as a write operation, 9.10 of the input data 301
Each data is a fractional part and is not written to the storage unit 33 because the circuit configuration is the same as the conventional one. Next, the output operation will be explained. By inputting the readout signal 306 to the output switching signal generator 13, the readout signal 306 is counted by a counter, and as shown in the timing diagram of FIG. A signal 102 is obtained. By inputting the output signal 102 to the output data latch section 11, the output of the output data shift register section 35 is held at the rising edge of the output signal 102. By inputting the output switching signal 102 to the output data switching section 12, when the output switching signal 102 is in a low state, the output of the output data shift register section 35 is changed to the output data 101.
When the output switching signal 102 is in a high state, the output of the output data latch unit 11 is output as the output data 101. As a result, among the output data 101 shown in the timing diagram of FIG. 2, each data from 1 to 8 is the output from the output data shift register 35 as in the conventional example, and 9 and 10 are the data immediately before the fractional part. 8 will be output.

As described above, according to this embodiment, the output switching signal generator 1
By controlling the output data latch section 11 with the output switching signal 102 output from the output data shift register section 35, the data immediately before the fractional part output from the output data shift register section 35 is held. The output data switching unit 12 causes the output data 101 to be output from the output data shift register unit 35 before the fractional part and output from the output data latch unit 11 for the fractional part. This eliminates the occurrence of an undefined state in the fractional portion of the output data 101.

Effects of the Invention As described above, according to the present invention, even when the number of output data is not a multiple of the number of S/P stages and has a fractional part in the read operation of a storage device, the output switching signal generator outputs the output switching signal. An output data latch section that uses the signal as a control signal holds the data immediately before the fractional part, and an output data switching section that also uses the output switching signal as a control signal outputs the output of the output data shift register as output data before the fractional part. However, in the fractional part, by outputting the output of the output data latch section as output data, the data in the fractional part is not output in an undefined state. For example, when processing a video signal, a fractional part occurs at the end of a horizontal scanning line, and if something equivalent to a horizontal synchronization signal is output as data for the fractional part, a shift occurs between horizontal scanning lines, but the fractional part If the data immediately before a portion is output as a fractional portion, there will be no shift between horizontal scanning lines, and an excellent storage device that can maintain data continuity can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a storage device in an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the embodiment of the present invention,
FIG. 3 is a block diagram of a conventional storage device, and FIG. 4 is a timing diagram showing the conventional operation. 11... Output data latch section, 12...
・Output data switching section, 13... Output switching signal generation section, 31... Input data shift register section,
32... Register section for storing input data, 33
. . . Storage section, 34 . . . Output data storage register section, 35 . . . Output data shift register section, 36 . . . Write signal generation section, 37
. . . Read signal generation section, 101 . . .
Output data, 102... Output switching signal, 301
...Input data, 302...Input reference clock, 303...Output data, 304...
...Output reference clock, 305...Write signal, 307...Read signal.

Claims (1)

[Claims] an output data latch section that receives the data output of the shift register section of the output section; an output data switching section that receives the data output of the shift register section and the output of the output data latch section; A storage device comprising: an output switching signal generator that outputs an output switching signal that controls data latch timing.