JPH0312962A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide electric characteristics in two or more states only with one semiconductor device by applying a signal to at least one of two gate electrodes to control a current flowing through a path communicating between source and drain regions. CONSTITUTION:Along a path connecting a source region 2 and a drain region 3, a first gate electrode 6a and a second gate electrode 6b connecting between both regions 2, 3 are coupled to the surface of a gate insulating film 5. Further, the source region 2, drain region 3, and gate electrodes 6a, 6b are protected by insulating films 7a, 7b. A current flowing through a path connecting between the source region 2 and the drain region 3 is controlled by a signal applied to the gate electrodes 6a, 6b. by selecting how to apply the voltage to the gate electrodes 6a, 6b a current between the source and drain 2, 3 can be changed stepwise in response to the number of the gate electrodes 6a, 6b. Hereby, electric characteristics in two or more states are assured with only one semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a device structure of a field effect transistor and a manufacturing method thereof.

[Conventional technology]

Figure 8 ta+h An example of a conventional field effect transistor?
FIG. FIG. 8 (al is the source region ((2
)% The drain region (3) and the gate electrode (6) are shown with the protective insulating film (7) removed. FIG.
Insulation model 1 (7), which was removed in , has been added. 8th
Figure (0) represents the symbol. In addition, Fig. 8 ta
l l-j N-channel MO8) transistor (enhancement type) is shown.

In FIG. 8 fb+, a source region (2) of an N-type semiconductor, and a semiconductor substrate Ill made of P-type silicon, and an N
A type semiconductor drain region ((3) is arranged at intervals of 1,000 mm and is surrounded by an insulating film called a field oxide film for element isolation) 4). A gate insulating film 5) is bonded to the surface of the semiconductor substrate jlI between the source region 1 (2) and the drain region (3j). A gate electrode (6) is formed on the surface of the gate insulating film +51.
are combined. The source region (2), the drain region 13), and the gate electrode (6) are covered with an insulating film +71. A hole (8) is drilled. An aluminum wiring electrode (9) is arranged in this contact hole (8).

In Figure 8+cl, D is drain'ik, F(3)
d.

G indicates the source electrode, and G indicates the gate electrode.

Further, FIGS. 9 til+ to 9 101 are cross-sectional views of elements shown in accordance with the steps in order to show the manufacturing method of the conventional device.

An insulating film (4) is placed on the P-type silicon semiconductor substrate (11)
1 is formed and the elements are separated. Thereafter, a gate insulating film 15), for example a silicon oxide film, is formed, and then a conductor (a part of which also includes the gate electrode), for example a polysilicon film, is formed on the surface of the gate insulating film 151, and then a conductive film 15) is formed on the surface of the gate insulating film 151. A resist 3υ is applied to the surface of the body □□□, and patterned by photolithography. A cross-sectional view of the state of the element formed through the steps up to this point is shown in the ninth figure.
FIG. 101.

Next, the conductor is etched as a patterned resist gll i mask, and the gate electrode (6) is etched.
is formed. Thereafter, an impurity such as arsenic is implanted into the P-type silicon semiconductor substrate (110) using ion implantation technology to form an N-type semiconductor source region (2) and an N-type semiconductor drain region (3). Ru. A cross-sectional view of the state of the element formed through the steps up to this point is shown in FIG.
It is 1.

Further, in order to protect the source region (2), drain region (3) and gate electrode 16), the insulating film 17) is OVD.
Laminated using technology. After that, the insulating film 17)
Contact holes (8) are formed in both of the above regions and above the gate electrode 16) using photolithography, and aluminum wiring electrodes (9) are formed.

A cross-sectional view of the state of the element formed through the steps up to this point is shown in FIG. 9 101.

Next, the operation will be explained.

In Fig. 8 f(1)l, +01, source 'city pole S
When grounded and a constant voltage VDIII is applied to the drain electrode, the voltage applied to the gate electrode GVc in this state,
That is, if the gate voltage VO is VG=0, the source region +(2) of the N-type semiconductor and the semiconductor substrate 11 of Pffu
) and the junction between the P-type semiconductor substrate III and the N-type semiconductor drain region 1 (3) separate the current, and the source -
No current flows between the drains. Next, when a voltage of 5 is applied to the gate electrode G, electrons are attracted to the surface head M of the P-type semiconductor substrate +11 in contact with the absolute R film +51, which is open between the source region 12) and the drain region 13). , the source region 2j of the N-type semiconductor and the drain region (3) of the N-type semiconductor are connected by the conductive layer of the N-type semiconductor, so that a current flows.

That is, this transistor is turned on.

The relationship between the gate voltage Vo and the current flowing between the drain and the source, that is, the drain current, is shown in FIG. 1θ.

In this way, the drain current can be controlled by the electric field generated by the voltage rC applied to the gate electrode G. One application of this electrical property is
Threshold value of gate voltage 7G? Set a voltage that exceeds this threshold value (high potential VH) or a voltage that is less than this threshold value (low potential VH).
l, ) (By applying i7, an ON state and an OFF state can be obtained, and a logic circuit can be constructed by associating logic 1.0 with each state. Configuration of this logic circuit An example will be explained with reference to FIGS. 11 and 12.

FIG. 11 shows an example of a logic circuit composed of three MO8 type transistors. MO8 type transistors Ml, M2.
M3 is coupled in series and the source of M3 is grounded. It is also connected to the drain M1 of Ml. Input signals V in l, Vin2 are M2, M3
is applied to gate terminals A and B of. The output point F is drawn out from the connection point between the source of Ml and the drain of M2, and the output voltage is -e-8+. The voltage VDD applied to the drain of M1uj is set to a value equal to or higher than the threshold value of the MO8 type transistor M1.

It is assumed that when a voltage equal to or higher than the threshold value of the MOS q transistors M2 and M3 is applied as each voltage of the input signals V in l and V in 2, M2 and M3 are turned on. At this time, V i n l , V
The voltage of in2 is VH (corresponds to truth table 1 shown later)
shall be. Conversely, %MOEI type transistors M2, M
Let the voltages of vtnl and Vin2 when 3 is in the OFF state be VL (corresponding to 0 in the truth table shown later).

In FIG. 11, VDD is applied and transistor M1
When the voltage VL is applied to Vinl and Vin2 when is in the ON state, the transistors M2 and M3 are turned OFF, and the output signal ve-2÷ of the output point F has a potential of VDD (later LLj 1 in the truth table shown +6) occurs. Also,
When voltage VH is applied to V j, n l and V i n 2, M2. Since M3 is in the ON state, the output point F
A potential ut of approximately 0 volts (15 vs. O in the truth table shown later) is generated in the output signal V 4 e+ of .

Similarly, VH for V in l and V' for V in 2.
When applying Lf and ■i n l, respectively, VL.

If a truth table is created assuming the case where VH is applied to V in 2, the result will be a %8 table.

(8) As can be seen from the truth table in Table 1, MOB type transistors M2 and M8 are both OFF and the output is ON, and M2. If either M8 is in the ON state, the output is in the ON state, and only when both M2 and M8 are in the ON state, the output is in the OFF state, and this logic circuit is a NAND
It will have a logical function. Also, Figure 12 shows MO8
Logic circuit composed of three type transistors [Problem to be solved by the invention] Since the conventional semiconductor device is configured as described above,
When the voltage applied between the source and the drain is set to a certain value, the drain current is controlled to flow in one state determined by a certain gate voltage.

I couldn't do it. For this reason, in order to improve the functionality of a semiconductor device, a large number of elements is required, and in order to achieve this, a large number of elements are required, making it impossible to achieve sufficient performance.

This invention was made to solve the above-mentioned problems, and by applying an arbitrary voltage to two or more gate electrodes, it is possible to control the electrical characteristics of one semiconductor device in two or more states. The purpose is to obtain a semiconductor device that can be obtained.

[Means to solve the problem]

In the semiconductor device according to the present invention, in order to control the current in the path connecting the source region and the drain region by a signal applied to the gate electrode, at least two gate electrodes are connected to the at least two gate electrodes connecting the gA regions. They extend side by side from one area to the other along two paths.

Further, at least two gate electrodes are arranged by dividing the path connecting the source region and the drain region.

In addition, in the step of forming an insulating film for element isolation on the above-mentioned Tosaki semiconductor device ff1H semiconductor substrate, and forming the entire gate insulating film, the gate insulating film is coated with Ti base 4', and a gate electrode is formed. The process of forming a semiconductor substrate, fully diffusing impurities into the surface of the semiconductor substrate to form a highly concentrated impurity diffusion layer that will become the source and drain regions, dividing the gate electrode into two or more parts, and fully insulating the divided gate electrodes. The device is manufactured by a manufacturing method including a step of forming an insulating wedge entirely on the element surface, and a step of forming wiring electrodes in the source region, drain region, and gate electrode.

[Effect]

In a semiconductor device configured as described above, a gate electrode is divided and arranged along a path connecting a source region and a drain region, and a voltage is applied to a semiconductor substrate surface area below the gate electrode. A conductive layer is induced. Therefore, when a certain voltage is applied between the source region and the drain region, by selecting the method of applying voltage to the divided gate electrodes, the current between the source and drain can be reduced by dividing the gate electrodes. It can be changed in stages depending on the number.

[Embodiments of the invention]

FIG. 1 is a plan view showing one embodiment of the present invention, and shows a source region 1 (2) and a drain region (
3), a first gate electrode (8al) and a second gate electrode (6b) are shown bonded to the surface of the gate insulating film +51, which connects both the singing regions. In FIG. 1, there are a source region 2), a drain region 13), and a gate electrode (8a).

Insulating film (7a) for protecting (6b) (7b
) is shown with the characters removed. Figure 1 1dl
, L indicates the gate length, Wl indicates the gate width of the first gate electrode, and W2 indicates the gate width of the second gate electrode. Figure 1 (+) 1 and Figure 1 (ol to Figure 1 tal
I-I' cross section of the embodiment of the present invention shown in and n
This is a sectional view taken at the -n' cross section, and the insulating film (7a) and +7bl removed in Figure 1 (8L1 are drawn (2)0). In the symbols shown, D is the drain electrode, S is the source electrode, G1 is the first gate electrode, and G2 is the second gate electrode.In this configuration, two types of transistors are arranged in parallel. In such a transistor, whose symbol is shown in FIG. 1, 1dl, the relationship between the gate widths of the ff1l gate electrode and the second gate electrode is W,
Assuming Wt, the relationship between 9 from the drain current and the first gate voltage VGI and the first gate voltage VG2 (from 5
-VGI, VG2 characteristics) are as shown in FIG. When the drain filler DK voltage VDst'' is applied and the voltage VGl is applied to the first gate electrode a 1vc and the voltage Vo2.fz is applied to the second gate electrode G2, the EI becomes more
-vol, vo2 characteristics become a curve ■ passing through point a.

In this state, if we set VO2,=0 and convert it to vax*y,
The 10-day-VGI characteristic is a curve (■) passing through point b. Conversely, if VGI-0 is set and VGg is changed, the I
The n5-VG2 characteristic is a curve (■) passing through the 0 point. From another perspective, when the voltage applied to the drain electrode is kept constant (VA), the voltage value applied to the first gate electrode G1 and the second gate electrode G2 is set as VA, and the voltage applied to the first gate electrode G1 and the second gate electrode G2 is set as VA. Turn on electrode G1 and second gate electrode 02.

By turning off the transistor, the value of s can be changed stepwise from a to b to c based on the drain current using one transistor. Does this mean that multiple electrical characteristics can be obtained with one transistor? It shows.

Figure 3 shows an application of the above-mentioned ability to obtain multiple electrical characteristics with one transistor, in which one conventional transistor and one transistor of the present invention are fully open and NOR is applied.
FIG. 3 is a diagram illustrating how a circuit can be configured. The part surrounded by the dotted circle is the transistor of the present invention. At this time, it is assumed that the relationship between the gate widths of the first gate electrode and the second gate electrode is Wl-W2. Input signal Vinl, V
i n 2 is in the ON state at the high potential VH, and the logic is 1.
It corresponds to At output point F, the voltage is ve-+f
-It is a parable.

If the configuration shown in Figure 3 of the main table is 0 night, the first gate electrode G1 and the second gate electrode G2 are
Only in the FF state, a high potential is generated at the circular signal (■) + total 4 at the output point F, so all the functions of the Nut t OR logic are performed. In this manner, the NOR circuit, which is composed of three transistors in the conventional device, can be composed of two transistors by using the transistor of the present invention.

Furthermore, in the above embodiment, an example of a transistor is shown in which two gate electrodes connect the source region (2) and the drain region (3) along a path connecting both regions. However, a similar effect can be expected from a transistor configured using a plurality of gates arranged by dividing the path connecting the above two ends. In the plan view shown, the path connecting the source region (2) and the drain region 3) is divided into two gate electrodes. This shows the case when combined. Figure 4+
In al, the source region + (2), the drain region (3) and the gate electrode (8a) (61)>k are shown with the protective insulating films (7a) (7b) removed. In FIG. 4 tal, W represents each gate width, Ll represents the gate length of the first gate electrode Gl, and L
, indicates the gate length of the second gate electrode G2. Fourth
Figure +bl is I of the embodiment of the present invention shown in Figure 4 tal.
This is a sectional view taken along the -I' section, and the insulation removed in FIG. 4 IJLI [(7a) and (7b) are added. Is Fig. 4 10) the present example? In the symbols shown, D indicates a drain electrode, S indicates a source electrode, Gl indicates a first gate pole, and G2 indicates a second gate electrode. the first gate electrode and the second gate electrode
It is assumed that the relationship between the gate lengths of the gate anode is, for example, Ll>L2. The +3-VGIVG2 characteristic in this case is shown in FIG.

In this case, when the same voltage is applied to the first gate electrode Gl and the second gate electrode G2 and the voltage is changed, the characteristics will be similar to that of a transistor having a gate length that is the sum of the gate lengths L1 and L. Obtainable. This current-voltage characteristic (ID.theta.-VG characteristic) is shown by a curve (2) passing through point a in FIG.

Next, when the voltage applied to the second gate electrode G2 is changed by α from the voltage applied to the first gate electrode G1, the drain current Ins changes. VG 2=VG l
-1-a, s flows more easily than the drain current, and as shown by the curve ■ passing from point a to point b above 8-
It becomes V a 1 characteristic.

Also, when VG2=vo1-α, the drain current IDS
is r# flow separation〈, and it becomes 5-VGIP# property as shown by the curve (■) passing from point a to point 0 below. For this reason, the voltage applied to the first gate terminal G I Vc is set to VGl=VA, and the first voltage of VG2 is V G 2 = V G 1, V
When G2=vo1+bo and VG2=V()l-υ, the current values at the fifth point, b point, and 0 point can be obtained.

As an application of this, the entire logic circuit can be constructed in the same manner as in the previous embodiment. FIG. 6 is an embodiment of the logic circuit, showing that a % circuit can be constructed from one conventional transistor. The part surrounded by the dotted circle is the transistor of the present invention. At this time, the relationship between the lengths of the porridge l gate electrode and the chloride 2 gate electrode is =L,
shall be. The input signals Vinl and Vin2 are in the ON state at a high potential vI (which corresponds to logic 1).

The output point is F, and the output point is 1 ml to 7 tfl. FIG. 7 1ml to FIG. . In the figure, (1) ~:
e+, (8), (9), 1(2)1.2z are the same as those shown in the cross-sectional view of the element in the manufacturing method of the conventional device.

Immediately, an insulating film (4) called a field oxide film is formed on the 2-layer semiconductor substrate Ill to isolate the elements. Thereafter, a gate insulating film (,5), for example, a silicon oxide film, is formed, and then a quadrielectric body 3011, for example, a polysilicon film, which includes a part of the gate electrode, is formed on the surface of the gate insulating film +51, and then the above-mentioned A resist circle is applied to the surface of the conductor and patterned using photolithography.

A cross-sectional view of the state of the element formed through the steps up to this point is shown in FIG.

Then buttered Regis)t,! 1)'The conductor (4)) is etched as a Q mask to form the gate electrode (6). Thereafter, an impurity, for example arsenic, is implanted into the surface of the semiconductor substrate 11) using an ion implantation technique to form an N-type semiconductor source region 2) and an N-type semiconductor drain region (3).

A sectional view of the state of the element formed through the steps up to this point is shown in FIG. 7 (b+).The above steps are the same as those of the conventional device.

Next, the resist t3tll is completely applied, and in order to completely divide the gate electrode 16), the photolithography technique i' is used to turn the gate electrode 16). A cross-sectional view of the state of the element formed through the steps up to this point is shown in FIG. 7 (10).

After that, as a patterned resist f mask,
The conductor which is the gate [electrode 1G) is etched to form divided gate electrodes (Ba) and (ab).

A cross-sectional view of the state of the element formed through the steps up to this point is shown in FIG. 7 1d-).

Next, an insulating film (7a), for example, a silicon film, is formed by heat treatment to insulate between the divided gate electrodes (6a), r6b), and further the source region), drain region 13) and gate electrode ( In order to protect 6a) and 6b, an insulating film (7b) is laminated by, for example, CvD technology. A cross-sectional view of the state of the element formed through the steps up to this point is shown in FIG. 7 (ei).

Thereafter, contact holes (8) are bored in the insulating films (7a), (7b) at the above-mentioned regions and above the gate electrodes (6a) (61)) by using the photo-S plate making technique. A wiring electrode (9) is formed. A cross-sectional view of the state of the element formed through the steps up to this point is shown in the seventh figure.
Figure tfl.

By the way, in the above explanation, we talked about the "%N channel MOS transistor (5 enhancement type)" station,
Needless to say, the present invention can also be used for other semiconductor devices.

〔Effect of the invention〕

Since the present invention is configured as described above, it achieves all the effects described below.

Electrical characteristics of two or more states in one element? As a result, logic circuits can be constructed with a small number of elements, and high integration of elements enables OI, and multiple outputs of intermediate values are possible instead of one output per element. Become.

Furthermore, a semiconductor device in which the gate electrode is divided can be manufactured by the semiconductor device manufacturing method of the present invention.

[Brief explanation of drawings]

FIG. 1 ta+ is a plan view showing an embodiment of the semiconductor device according to the present invention, FIG. 1 fb+ and FIG. 2 is a diagram showing all the electrical characteristics of an embodiment of this invention device, FIG. 3 is a diagram of a NOR circuit using one embodiment of this invention device, and FIG. 4 is a diagram showing the symbols of one embodiment of this invention device. tlllll
A plan view showing another embodiment of the device according to the invention, FIG. 4 ib
+ is a sectional view of another implementation row of this invention device, Fig. 4 +c)
5 is a diagram showing the symbols of another embodiment of the device of this invention, and FIG. 5 is a diagram showing the electrical characteristics of another embodiment of the device of this invention. FIG. 6 shows another embodiment of this inventive device F! A diagram of a NAND circuit using AJ'fr, FIG. 7 is a cross-sectional view of a semiconductor device in each step of the method for manufacturing a semiconductor device of the present invention, and FIG.
al is a plan view of a conventional semiconductor device, FIG. 8 11) is a cross-sectional view of a conventional semiconductor device, FIG. A cross-sectional view of a semiconductor device at each step of the manufacturing method, Figure 1θ is a diagram showing the electrical characteristics of a conventional semiconductor device, Figure 11 is a diagram of a NAND circuit using a conventional semiconductor device, and Figure 12 is a diagram of a conventional semiconductor device. FIG. 3 is a diagram of a NOR circuit using the device. In the figure: 11 is a semiconductor substrate, (2) is a source region, + (3) is a drain region, (41 is an insulating film, +51 is a gate insulating film, (8a), (6b) a Vi gate electrode,
C'ia) (71)) is an insulating film and (9) is a wiring electrode. In addition, the same reference numerals in each figure indicate the same or equivalent parts f0

Claims (3)

[Claims] (1) a source region and a drain region; at least two gate electrodes extending side by side from one region to the other along at least two paths connecting these regions; A semiconductor device characterized in that a signal is applied to at least one of the regions to control a current in a path connecting both of the regions. (2) A source region, a drain region, and at least two gate electrodes disposed to separate a path connecting these two regions, and a signal is applied to all of the gate electrodes to connect the two regions. A semiconductor device characterized by controlling a current in a path. (3) Forming an insulating film for element isolation on the semiconductor substrate,
A process of forming a gate insulating film, a process of bonding a conductor to the gate insulating film to form a gate electrode, a process of diffusing impurities on the surface of a semiconductor substrate to form a highly concentrated impurity diffusion layer that will become a source region and a drain region. , a step of dividing the gate electrode into two or more and insulating between the divided gate electrodes, a step of forming an insulating film on the element surface, and a step of forming wiring electrodes in the source region, drain region, and gate region. A method for manufacturing a semiconductor device.