JPH0313009A - Analog digital converter - Google Patents

Abstract

PURPOSE:To improve the resolution as a final output by detecting the polarity of an analog signal, applying absolute value processing to the said analog signal and boosting a maximum output voltage of the analog signal subject to absolute value processing up to a full scale voltage to an analog digital conversion section. CONSTITUTION:An analog signal AS (such as + or -2.5V) is fed to a most significant bit comparator 1 and an absolute value circuit 2. The most significant bit comparator 1 detects the polarity of the analog signal AS shown in figure (a) based on a reference voltage VREF (0V). The analog signal AS is converted into only a positive component of 0-2.5V shown in figure (b) based on the reference voltage VREF in the absolute value circuit 2. Then an output voltage from the absolute value circuit 2 is fed to an amplifier 3, in which the signal is amplified into a signal of 0-5V shown in figure (c). The signal of 0-5V is fed to an A/D converter section 4, in which the signal is converted into a 3-bit digital signal DS. Then the digital signal DS is fed to a latch circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an analog-to-digital converter suitable for use in converting an analog signal into a digital signal.

"Prior Art" In conventional analog-to-digital converters, the most significant bit represents the positive or negative of the analog quantity. For example, OB (
When using offset binary) code, the fourth
As shown in the figure, when the analog quantity is Ov or positive, the most significant bit is set to 1°°, and all bits of the pond represent the absolute value, and when the analog quantity is a negative value, the most significant bit is set to "0".
and the other bits represent the absolute value. In this figure, the resolution of the analog-to-digital converter is assumed to be 3 bits to simplify the explanation.

[Problems to be Solved by the Invention] In the conventional analog-to-digital converter described above, the resolution (number of bits) of the analog-to-digital converter is determined by the voltage resolution of the internal comparator of the A/D converter and the input voltage range (full range). scale). That is, the accuracy of ILsB (least significant bit) is approximately 0.62V as shown in FIG. Furthermore, if the voltage resolution of the internal comparator in this case is, for example, 0.70V, then in such an analog-to-digital converter, the resolution of the A/D conversion section is simply set to 4 bits (in this case, ILSB
Even if you try to change the accuracy to about 0.31V),
It cannot be identified with the voltage resolution (0.70V) of the internal comparator. As a result, in the conventional analog-to-digital converter, a problem arises in that the number of bits cannot be increased beyond the voltage resolution of the A/D converter, that is, the resolution as a final output cannot be increased.

This invention was made in view of the above-mentioned problems, and is
It is an object of the present invention to provide an analog-to-digital converter that can increase the number of bits without changing the voltage resolution of the D conversion section and improve the resolution of the final output.

"Means for Solving the Problems" In order to solve these problems, the present invention includes a detection circuit that detects the positive/negative state of an analog signal, an absolute value circuit that performs full-wave rectification of the analog signal, and two an amplifier circuit that has twice the amplification degree and amplifies the full-wave rectified analog signal; an analog-to-digital converter that converts the analog signal from the amplifier circuit into a digital signal of predetermined bits; It is characterized by comprising a latch circuit that outputs positive and negative signals as the most significant bits and outputs the predetermined bits as the lower bits thereof.

"Operation" First, an analog signal is supplied to the detection circuit and the absolute value circuit. The detection circuit detects whether the analog signal is positive or negative based on the reference voltage, and the positive or negative signals are supplied as the most significant bits to the latch circuit.

Further, in the absolute value circuit, an analog signal is converted into an analog signal having only positive voltage components based on a reference voltage. The output voltage from this absolute value circuit is amplified twice by an amplifier circuit. The analog signal from the amplifier circuit is then supplied to an analog-to-digital converter, where it is converted into a digital signal of predetermined bits. and,
This digital signal is supplied to a latch circuit.

The latch circuit latches and outputs the positive and negative signals from the above-mentioned detection circuit and the digital signal from the analog-to-digital converter at a predetermined timing.

"Embodiments" Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In this figure, 1 is a comparator for the most significant bit, and when the analog signal AS is supplied to one input terminal and the reference voltage VREF (OV) is supplied to the other input terminal,
It is designed to operate as a zero cross detector.

2 is an absolute value circuit, which receives an analog signal AS that goes from positive to negative.
is full-wave rectified to make only the positive voltage component. Reference numeral 3 denotes an amplifier, which doubles the output voltage of the absolute value circuit 2 to raise the maximum voltage of the analog signal up to the full-scale voltage of the A/D conversion section, which will be described later.

4 is an n-bit A/D converter, and the reference voltage v[18
The output voltage of the amplifier 3 is converted into an n-bit (for example, 3-bit) digital signal DS based on the signal F. Reference numeral 5 denotes a latch circuit, which takes the positive/negative signal that takes two states of "0" or "1" from the most significant bit comparator 1 as the most significant bit, and outputs the n-bit digital signal from the A/D converter 4. The signal DS is output as its lower bits (digital signal DS-, 4 bits).

In addition, the above-mentioned most significant bit comparator 1 absolute value circuit 2. Amplifier 3. A/D converter 4. The latch circuit 5 and the reference voltage resistor are connected to the same I-I to eliminate time errors.
It is formed on a C (integrated circuit) substrate.

Next, the operation of this embodiment with the above configuration will be explained.

First, the analog signal AS shown in FIG. 2(a) (for example,
±2.5V) is supplied to the most significant bit comparator 1 and absolute value circuit 2. The most significant bit comparator 1 detects whether the analog signal As is positive or negative based on the reference voltage VIIEF (0■). That is, when the analog signal AS is equal to or higher than QV (positive value), "1" is output from the most significant bit comparator 1, and when it is negative, "0" is output. A signal of "0" is supplied to the latch circuit 5 as the most significant bit.

In addition, in the absolute value circuit 2, the analog signal AS is set to 0 to 2.5 as shown in FIG. 2(b) based on the reference voltage VRIF.
It is converted into a signal containing only the positive component of v. The output voltage from the absolute value circuit 2 is then supplied to the amplifier 3 as shown in Fig. 2 (
It is amplified to a signal of 0 to 5v shown in C). This 0~5■
The signal is supplied to the A/D converter 4, where it is converted into a 3-bit digital signal DS as shown in FIG. In this case, the voltage resolution of the internal comparator of the A/D converter 4 is the same as before, but since the voltage corresponding to a half cycle of the analog signal AS is converted into a 3-bit digital signal DS, The accuracy of ILsB corresponds to 0.31V. And this digital signal DS
is supplied to the latch circuit 5.

Next, in the latch circuit 5, the positive and negative signals from the most significant bit comparator 1 mentioned above are treated as the most significant bit, and A
The digital signal DS from the /D converter 4 is latched as its lower bit at a predetermined timing and output as a 4-bit digital signal DS=.

As described above, in this embodiment, the analog signal AS, which conventionally represented the absolute value of an analog quantity with 2 bits, can now be represented with 3 bits without changing the voltage resolution of the A/D converter 4. , the accuracy of ILSB can be doubled.

"Effects of the Invention" As explained above, according to the present invention, the positive and negative states of an analog signal are detected, the absolute value of the analog signal is converted, and the maximum output voltage of the absolute value of the analog signal is converted into an analog signal. By increasing the voltage up to the full scale voltage of the digital converter, the number of bits can be increased without changing the voltage resolution of the analog-to-digital converter, thereby providing the advantage of increasing the resolution of the final output.

[Brief explanation of drawings]

FIG. 1 is a book diagram showing the configuration of an embodiment of the present invention, FIGS. 2(a) to (C) and 3 are waveform diagrams for explaining the operation of the embodiment, and FIG. The figure is a waveform diagram for explaining the operation of a conventional analog-to-digital converter. l... Comparator (detection circuit) for the most significant bit 2... Absolute value circuit, 3... Amplifier (
amplifier circuit), 4... A/D conversion section (analog-digital conversion section), 5... latch circuit. (0) (b) tc)

Claims (1)

[Claims] a detection circuit that detects positive/negative of an analog signal; an absolute value circuit that full-wave rectifies the analog signal; and an amplifier circuit that has a double amplification degree and amplifies the full-wave rectified analog signal; an analog-to-digital converter that converts the analog signal from the amplifier circuit into a digital signal of predetermined bits;
An analog-to-digital converter comprising: a latch circuit that outputs positive and negative signals from the detection circuit as the most significant bits and outputs the predetermined bits as the lower bits thereof.