JPH03130141U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a timer according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the timer. 2... Microcomputer, 2a... External set value input means, 2b... Correction means, 2ab... Internal setting means, 2c... Comparison means, 2d... Main counting means, 2e... Sub counting means, 4... ...External setting means, 10...Start signal input circuit, 14...
...Mechanical relay (object).

Claims (1)

[Scope of Claim for Utility Model Registration] A device comprising an external setting means 4, internal setting means 2a, 2b, main counting means 2d, comparison means 2c, and sub counting means 2e, wherein the external setting means 4 is configured to adjust the timer time. is set by external operation, and outputs the timer time as an external set value Td, and the internal setting means 2a and 2b subtract a predetermined delay time Tr from the external set value Td. It outputs the time value as the internal setting value Tc,
Further, the delay time corresponds to the operation delay time from when the target object 14 whose operation is controlled in response to the output of the timer inputs the timer output until it starts the operation, and the main The counting means 2d starts the counting operation from the timer start and outputs the counted value Te, and the comparing means 2c calculates, when the counted value Te of the main counting means 2d matches the internal setting value Tc, The matching output is outputted as an operation output for the object 14, and the sub-counting means 2e performs a counting operation from the time when the operation output is input to the object 14 until it starts operating. A timer characterized in that it outputs a numerical value Tr to internal setting means 2a and 2b for a predetermined delay time.