JPH0466745U

JPH0466745U -

Info

Publication number: JPH0466745U
Application number: JP11011690U
Authority: JP
Priority date: 1990-10-19
Filing date: 1990-10-19
Publication date: 1992-06-12

Description

[Brief explanation of the drawing]

第１図は本考案の実施例にかかるタイマの回路
ブロツク図、第２図および第３図は該タイマの動
作説明に供するフローチヤートである。１……マイクロコンピユータ、２……設定手段
、４……サブ計数手段（測定手段）、５……補正
手段、６……メイン計数手段、７……比較手段、
１５……他のタイマ。 FIG. 1 is a circuit block diagram of a timer according to an embodiment of the present invention, and FIGS. 2 and 3 are flowcharts for explaining the operation of the timer. 1...Microcomputer, 2...Setting means, 4...Sub counting means (measuring means), 5...Correction means, 6...Main counting means, 7...Comparing means,
15...Other timers.

Claims

[Claims for Utility Model Registration] Comprising a setting means 2, a measuring means 4, a correcting means 5, a counting means 6, and a comparing means 7, the setting means 2 is for inputting and setting a set timer time through a setting operation. In the measurement mode preceding the normal operation mode, the measuring means 4 calculates the output power of another timer 15 having the same set timer time as the set timer time inputted from the setting means 2. ,
The correction means 5 measures in advance the amount of deviation in timer time between the other timer 15 and the same set timer time, and the correction means 5 adjusts the set timer input by the setting means 2 in the normal operation mode. time so that there is no discrepancy between the set timer time and the timer time of the other timer 15,
The correction is made based on the amount of deviation measured in advance by the measuring means 4, and the counting means 6 starts counting operation in response to a start signal and outputs the counted value as elapsed timer time. A timer characterized in that the comparing means 7 outputs a timer output when the set timer time corrected by the correcting means 5 and the elapsed timer time match.