JPH0313068A - Noise reduction circuit - Google Patents

Abstract

PURPOSE:To decrease number of CCD delay elements and to reduce the cost by using a 1H delay circuit using a line correlation noise canceller for the constitution of a luminance signal comb-filter. CONSTITUTION:A reproduced luminance signal is given to a noninverting input of a 1st subtractor 20 and a 1H delay circuit 16 comprising a CCD and a noninverting input of a 2nd subtractor 24. The 1H delay circuit 16 constitutes a single delay means, 1st-4th subtractors 20, 24, 30, 38 constitute 1st-4th calculation means and a switch 42 constitutes a switch means. A difference between the reproduced luminance signal retarded by 1H at the 1H delay circuit 16 and a signal not retarded, that is, a noise component without line correlation is extracted as an output of the 1st subtractor 20 and a large level in the noise component, that is movement component in the picture is subjected to amplitude limit by a limiter 22 forming the 1st control means and subtracted from the input reproduction luminance signal via a trap circuit 40 and the switch 42.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a noise reduction circuit that processes a luminance signal in a video signal, and particularly to a noise reduction circuit that processes a luminance signal in a video signal. This invention relates to improvements in circuits that perform processing such as correlated noise cancellation.

[Prior art] VTR, which is a recording and reproducing device that records and reproduces video signals.
The reproduction system is equipped with a line correlation noise canceling circuit that reduces noise by vertical correlation of images, and the noise canceling circuit is configured to cancel the noise by a control signal indicating whether the mode is standard speed (SP) mode or long time (EP) mode. The reproduced brightness signal is switched to go through the circuit or bypass it.
The luminance signal is fed to the comb filter.

FIG. 2 is a block diagram of a reproducing system of a recording/reproducing apparatus including such a circuit portion. In the figure, a line correlation noise canceling circuit (hereinafter referred to as a line correlation noise canceller) 10 is supplied with a reproduced luminance signal that is FM demodulated after being reproduced from a video tape, and when the EP mode is used, the luminance signal is used via a switch SW. The signal is applied to a comb filter 14.

The switch SW is switched by a signal indicating the two speed modes 5PSEP, and the line correlation maze canceller 10 is bypassed by the bypass circuit 12 in the SP mode. A luminance signal Y is obtained at the output terminal of the luminance signal comb filter 14, and is combined with a color signal C as necessary to form a color composite video signal. Incidentally, when it is desired to use the luminance signal Y' before passing through the luminance signal comb filter 14, it is extracted as shown by the dotted line in the figure.

FIG. 3 is a block diagram showing the configuration of a noise reduction circuit including the line correlation noise canceller 10, the bypass circuit 12, the switch SW, and the luminance signal comb filter 14 in the reproduction system shown in FIG.

The line correlation noise canceller IO is an IH consisting of a CCD.
Delay circuit (DL) 16, LPF 18, subtracter 20
．． 24, limiter 22, while the luminance signal comb filter 14 has an IH delay circuit 26 consisting of a CCD,
It has an LPF 28, a subtracter 30.38, a BPF 32, a limiter 34, and a delay compensation circuit 36 for time adjustment.

[Problems to be Solved by the Invention] In the conventional reproduction system noise reduction circuit described above, a relatively expensive IH delay element using a CCD is required for both the line correlation noise canceler and the next-stage luminance signal comb filter.

Therefore, it is an object of the present invention to provide a low-cost noise reduction circuit with a circuit configuration in which the number of IH delay elements using CCDs is reduced.

[Means for Solving the Problems] In the present invention, in order to achieve the above object, the IH delay element in the line correlation noise canceler is also used in the configuration of the luminance signal comb filter. This is based on the fact that although there is a difference in the gain and band of the limiter between the two structures, the combination of the IH delay element and the subtracter has the same circuit configuration and the same operation.

That is, according to the present invention, a delay means responsive to an input video signal, a first arithmetic means for subtracting an output signal of the delay means from the input video signal, and a first arithmetic means for limiting the amplitude of the output signal of the first arithmetic means. a second arithmetic means for subtracting the output signal of the first limiter from the input video signal; and a third arithmetic means for subtracting the output signal of the delay means from the output signal of the second arithmetic means. , a second limiting means for limiting the band and amplitude of the output signal of the third computing means, and a fourth computing means for subtracting the output signal of the second limiting means from the output signal of the second computing means. A reduction circuit is provided.

[Function] In the noise reduction circuit of the present invention, the first and second delay means are made into a single unit, so instead of configuring the line correlation noise canceler and the luminance signal comb filter separately as in the conventional circuit configuration, they are combined. This is an integrated circuit configuration. Therefore, it is sufficient to use only a single CCD delay element, which simplifies the circuit configuration.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the noise reduction circuit of the present invention. This circuit configuration can be used in place of the conventional example shown in FIG. 3, and therefore, as shown in FIG. given, output terminal OU
T is used in the same way as the output terminal of the luminance signal comb filter 14.

The reproduced luminance signal that entered the input terminal is an IH composed of a CCD.
It is applied to the delay circuit 16, the first subtractor 20, and the second subtractor 24. The output signal of the IH delay circuit 16 is applied to the first subtractor 20 and the third subtractor 30 via the L P F 18.

The output signal of the first subtracter 20 is transmitted to the second subtracter 24 via a limiter 22, a trap circuit 40, and an open/close switch 42.
given to the power of one person. The output signal of the second subtractor 24 is combined with the output signal of the third subtractor 30 and the delay compensation circuit 36 for time adjustment.
given to. The output signal of the delay compensation circuit 36 is given to the ten input of the fourth subtracter 38, and the output signal of the third subtracter 30 is given to the fourth subtracter 3 via the BPF 32 and the limiter 34.
8 is given to one person's power. The output signal of the fourth subtracter 38 is applied to the output terminal OUT.

The IH delay circuit 16 constitutes the single delay means, the first to fourth subtracters 20, 24, 30, and 38 constitute first to fourth calculation means, respectively, and the switch 42 constitutes a switch means. It consists of Note that the first and third subtracters 20
．． If the input polarity of 30 is opposite to that shown, the second,
The fourth subtractor can be replaced with an adder.

The trap circuit 40 is a band stop filter having characteristics opposite to those of the BPF 32, and performs band compensation by blocking passage of color signal components.

The circuit of FIG. 1 operates as follows. IH delay circuit 16
The difference between the IH-delayed reproduced luminance signal and the non-delayed signal, that is, the noise component without line correlation, is detected by the first subtractor 2
It is taken as an output of 0.

The amplitude of the noise component with a high level, that is, the motion component in the image, is limited by the limiter 22 constituting the first limiting means, and the trap circuit 40. It is subtracted from the input reproduced luminance signal via the switch 42.

Here, the switch 42 is turned ON10 F F by a control signal indicating the SP mode or EP mode, which is the operating mode of a recording/reproducing (or only reproducing) device such as a VTR.
For example, it is conductive in EP mode and non-conductive in SP mode. Therefore, the second subtracter 24 performs the above subtraction operation only when the switch 42 is ON, and when it is OFF, the input reproduced luminance signal is output as is. The above-mentioned IH delayed signal is subtracted from the output signal of the second subtractor 24 by the third subtractor 3o, and the difference between the two is extracted. BPF32 has a color subcarrier frequency (3.58 MI at N T S C)
Z) as the center frequency, the noise component in the color signal band is extracted and the limiter 34 limits the amplitude, and then the output of the second subtracter 24 is subtracted from the delayed signal for time adjustment. It forms a comb filter.

The BPF 32 and limiter 34 constitute a second limiting means.

By the above operation, the luminance signal Y that has passed through the luminance signal comb filter is obtained from the output terminal OUT, but as explained in Fig. 2, when you want to extract the luminance signal Y° that does not pass through the luminance signal comb filter , second subtractor 2
This can be taken out from the output terminal 4 as shown by the dotted line in FIG.

Although the trap circuit 40 and the switch 42 are used in the above embodiment, these circuits can be omitted, and in that case, the output of the limiter 22 is applied to the second subtracter 24.

[Effects of the Invention] As is clear from the above detailed explanation, the noise reduction circuit of the present invention has a circuit configuration in which the IH delay circuit used in the line correlation noise canceler is also used as the configuration of the luminance signal comb filter. Therefore, cost reduction can be achieved by reducing the number of CCD delay elements, and when providing a switch to bypass the line correlation noise canceller, a simple 0N10FF type switch can be used.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the noise reduction circuit of the present invention, Fig. 2 is a block diagram of a conventional VTR playback system, and Fig. 3 is a block diagram of the vicinity of the line correlation noise canceler in Fig. 2. . 16... IH delay circuit, 18... LPF, 2
0.24.3038...Subtractor, 22.34...
Limiter, 32...BPF. 36... Delay compensation circuit, 40... Trap circuit,
42...Switch.

Claims (3)

[Claims] (1) Delay means responsive to an input video signal, first calculation means for subtracting the output signal of the delay means from the input video signal, and first limiting means for limiting the amplitude of the output signal of the first calculation means a second arithmetic means for subtracting the output signal of the first limiting means from the input video signal; a third arithmetic means for subtracting the output signal of the delay means from the output signal of the second arithmetic means; 3. second limiting means for limiting the band and amplitude of the output signal of the third computing means; and fourth limiting means for subtracting the output signal of the second limiting means from the output signal of the second computing means.
A noise reduction circuit comprising calculation means. (2) The noise reduction circuit according to claim 1, further comprising a trap circuit having a color subcarrier as a center frequency provided between the first calculation means and the second calculation means. (3) Claim 1 or 2, further comprising a switch means for conducting or non-conducting between the first calculating means and the second calculating means.
Described noise reduction circuit.