JPH03130841A - Back-up device for development of microcomputer - Google Patents

Abstract

PURPOSE:To actuate an execution interrupting function even though the processing speed of a microcomputer is increased and therefore the bus cycle time is reduced by detecting the coincidence among plural series. CONSTITUTION:The latch circuits 2a and 2b latch the state output signal D1 of a microcomputer 10. Then a pair of coincidence detection parts 20a and 20b contain the coincidence detection circuits 4a and 4b which compare the latch output signals D3a and D3b with the execution interruption conditions D8 and outputs the coincidence signals. A coincidence signal selection circuit 9 selects the coincidence signal of the part 20a or 20b. A control circuit 7 outputs the control signals to the parts 20a and 20b as well as to the circuit 9. Thus it is possible to secure the full processing time for an execution interruption function even though the processing speed of the microcomputer 10 is increased and therefore the bus cycle time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer development support device, and more particularly to a microcomputer development support device having an execution interrupt function.

[Conventional technology]

Conventional development support equipment for microcomputers is
By having one set of match detection units, the execution interruption function was realized.

FIGS. 3 and 4 are a block diagram of an example of a conventional microcomputer development support device and a timing chart for explaining its operation.

The microcomputer 10 performs a microcomputer bus cycle (T+, Tz---Tn) at time T, outputs a status output signal t hours after the start of each bus cycle, and outputs an execution interrupt signal. Assume that DI8 is input at the end of the bus cycle. Also, S in the timing diagram. is the status output signal data of bus cycle T0, and In is the status output signal S. B is the bus
Let it represent the execution interruption signal data of cycle T0.

The status output signal D6 outputted from the microcomputer 10 is latched by the latch circuit 4 of the coincidence detection section 20 at the beginning of a bus cycle by the control signal D6 outputted from the control circuit 27. -The number output circuit 4a is the child circuit 4.
It will be output from

The checked state output signal D3 is inputted, compared with a preset execution interruption condition D8, and the result is outputted as a match signal D5 after a certain delay time of the circuit. The execution interruption signal generation circuit ii inputs the coincidence signal R, changes it into an execution interruption signal DIl+ suitable for the execution interruption input means of the microcomputer, and supplies it to the microcomputer 10.

In this case, the execution interrupt signal D is sent from the latch circuit 24 of this circuit.
The total processing time in the trench that outputs I8 must be less than or equal to the bus cycle time (T).

[Problem to be solved by the invention]

In the conventional microcomputer development support device mentioned above,
As the bus cycle time (T) decreases due to the recent increase in the processing speed of microcomputers, there has been a drawback that the entire processing time for the execution interrupt function cannot be secured.

[Means to solve the problem]

The microcomputer development support device of the present invention is a development support device for a microcomputer having an address first-out function and an execution interrupt input means, and includes a latch circuit for a status output signal of a microcomputer, a latch output signal, and a preset latch circuit. a pair of coincidence detection sections each having a coincidence detection circuit that compares the execution interruption conditions and outputs a coincidence signal; and a coincidence signal selection circuit that selects one of the plurality of coincidence signals output from each of the plurality of coincidence sections. and a control circuit that outputs a control signal to the pair of coincidence detection sections and a coincidence signal selection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Status output signal D of the microcomputer 10! Two latch circuits 2a r 2b that latch, latch output signals D3a and D3b, and a preset execution interruption condition D8.
Two sets of coincidence detecting sections 20. and 4.2 consist of coincidence detection circuits 4a + 4b which compare the coincidence signals D3a and D3b and output coincidence signals D3a and D3b. ,2
0b, and a coincidence signal selection circuit 9 that selects one of the coincidence signals D5a r D5b output from each of the negative number peak parts 20a and 20b, and a coincidence signal selection circuit 9 that selects one of the coincidence signals D5a and D5b output from the two sets of coincidence detectors 20a and 20b and the coincidence signal selection circuit 9. Control signal D6a ) D6b +
It consists of a control circuit 7 which alternately outputs DI7, and an execution interruption signal generation circuit 11 which inputs the selected coincidence signal DIO and changes it into an execution interruption signal DI8 in accordance with the execution interruption input means of the microcomputer.

Next, the operation of the process shown in FIG. 1 will be explained using the timing chart shown in FIG.

Since the microcomputer 10 is the same as the conventional microcomputer IO shown in FIG. 3, the control signals 6a+6b outputted from the control circuit 7 at the same time as the outputs are latched alternately in the latch circuits 2a+2b. At this time, the latch circuit 2a of the minus number peak portion 20a receives the state output signal Dl that was output earlier in the bus cycle Tne (ne=even number).
The latch circuit 2b latches the bus cycle Tne
+ 1 (ne = even number) first-out status output signal.

Latch. The respective latch output signals D3a and D3b latched in this way are -number output circuit 4a+
4b, it is compared with the execution interruption condition D8, and after a certain delay time of the circuit, match signals D5a and D5b are output. The match signals D5a and D5b are input to the match signal selection circuit 9, selected by the control signal D17 from the control circuit 7, and the execution interrupt signal DIG is supplied to the execution interrupt signal generation circuit 11.

For example, in the timing diagram of FIG. 2, when the control signal DI7 is "0", the match signal D5a is selected, and when it is "1", the match signal I)sb is selected.

The execution interruption signal generating circuit 11 supplies the execution interruption signal D8 to the microcomputer 11 in accordance with the execution interruption input means of the microcomputer 10.

In this case, the processing time in the case that outputs the execution interruption signal D18 from the latch circuits 2a+2b of this embodiment is at most the bus
The cycle time (T) becomes the child state output signal advance time (1), which corresponds to higher speed.

〔Effect of the invention〕

As is clear from the above explanation, since the microcomputer development support device of the present invention detects coincidence of multiple series, the processing speed of recent microcomputers is increased and the pass cycle time is reduced. The execution interruption function also has the effect of responding.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of the blocks in FIG. 3. 2a+2b...Latch circuit, 4a+4b...
....-number circuit, 7... control circuit, 9.
. . . Match signal selection circuit, 10 . . . Microcomputer, 11 . . . Execution interruption signal generation circuit, 20a, 20b .
... Status output signal, D3a, D3b... Latch output signal, D5a, D5b... Match signal,
D8+DI7'+Dl8...Control signal, D
8... Execution interruption condition.

Claims (1)

[Claims] In a development support device for a microcomputer having an address advance function and an execution interruption input means, a latch circuit for a status output signal of the microcomputer compares the latch output signal with a preset execution interruption condition and outputs a match signal. a pair of coincidence detection sections having a coincidence detection circuit; a coincidence signal selection circuit that selects any one of the plurality of coincidence signals outputted from each of the coincidence detection sections; and the pair of coincidence detection sections and a coincidence signal selection circuit. A microcomputer development support device that is specially designed to include a control circuit that outputs control signals to the computer.