JPH08307405A - Frame synchronism detection device - Google Patents

Abstract

PURPOSE: To provide a frame synchronism detection device which can detect a frame synchronism pattern of the PCM serial data by means of a slow CMOS element and with no use of a fast ECL element. CONSTITUTION: The PCM bit serial data are converted into the 1-word/8-bit word serial data by an 8-bit shift register 1. Then the word serial data undergo the sequential word shift through the word latches L1 to L4 and are fetched in every word by these latches. All parallel bits bl to b31 of latches L1 to L4 are shifted by one bits and every 24 bits of the frame synchronous pattern length and then divided into 8 pairs of bit lengths (b1 to b24, b2 to b25,..., b8 to b31). These 8 pairs of bit patterns are inputted to the frame synchronism parts F1 to F8 respectively, and a frame synchronism pattern is detected. Thus it is possible to detect the frame synchronism at a speed of 1/8 bit rate of the PCM serial data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization detecting device, and more particularly to a frame synchronization detecting device for monitoring frame information transmitted bit serially and detecting a frame synchronization pattern included therein.

[0002]

2. Description of the Related Art Cueing of a frame of a PCM bit serial signal is performed by detecting a frame synchronization pattern indicating the beginning of the frame. A conventional method of detecting this frame synchronization pattern will be described with reference to FIG. In FIG. 3, the PCM bit serial signal is input to the shift register 1 and converted into a parallel signal having a frame synchronization pattern length.

This parallel conversion output is compared with a known frame synchronization pattern serving as a reference in the coincidence detecting section 3, and the comparison result is input to the error bit number calculating section 4. In the error bit number calculation unit 4, the number of mismatched bits is counted as an error bit, and the count result is output to the frame synchronization determination unit 5. If the number of error bits is equal to or greater than a preset value, the frame synchronization determination unit 5 determines that the synchronization pattern is not a synchronization pattern, and the next 1
The parallel data shifted by bits is compared with a known frame sync pattern.

The above operation is repeated until the number of error bits becomes smaller than the set value, and when the number of error bits becomes smaller than the set value, the frame synchronization pattern is detected from the frame synchronization determination section 5. Various frame timing signals, word timing signals, latch timing signals, etc. indicating that are generated.

The serial register and latch 2 are for sequentially taking in PCM bit serial data and converting it into word serial data. When the frame synchronization is detected by the frame synchronization determining section 5, accurate word serial data is sequentially output thereafter. It is supposed to do.

[0006]

In the conventional frame synchronization detecting device shown in FIG. 3, since the frame synchronization determination is made every time one bit of the PCM bit serial signal is input, the determination operation is performed. It must be performed within the time interval of one bit of the PCM serial signal. Therefore, when the PCM signal has a high bit rate, it is necessary to configure the circuit with, for example, an ECL (emitter coupled logic) element having extremely high speed, which is disadvantageous in that it is expensive.

An object of the present invention is to detect C even when detecting frame synchronization of a PCM signal having a high bit rate.
It is an object of the present invention to provide a frame synchronization detecting device that enables the use of elements such as MOS operating at a standard speed.

[0008]

According to the present invention, there is provided a frame synchronization detecting device for monitoring frame information transmitted bit-serially and detecting a frame synchronization pattern included in the frame information. Word serial conversion means for converting a word serial signal of word n bits (n is an integer of 2 or more), a plurality of word latch means for sequentially latching the word serial signal in word units, and parallel output bits of the latch means. Of the n bit combination patterns having the same number of bits as the number of bits of the frame synchronization pattern and different from each other, the comparison means compares n sets of bit combination patterns with the reference frame synchronization pattern. A frame synchronization detection device characterized by detecting synchronization is obtained. It is.

[0009]

The PCM bit serial data is converted into 1-word n-bit word parallel data by the shift register, and the frame synchronization pattern is detected by the converted word parallel data. In this case, there is uncertainty as to which position in the parallel data the start bit start position of the frame synchronization pattern to be detected is. In order to remove this uncertainty, as many frame synchronization detection units as there are patterns that appear indeterminately are provided.

That is, in order to reduce the operation speed to 1 / n with 1 word n bits, PCM bit serial data is converted into 1 word n bits of word parallel data, and n
A number of frame sync detectors are provided, and in these n frame sync detectors, n sync patterns that appear indefinitely are simultaneously detected to reduce the operation speed to 1 / n of the PCM bit rate.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same portions as those in FIG. 3 are designated by the same reference numerals. still,
In the present embodiment, the case where the sync pattern length is 24 bits and the operation speed is reduced to 1/8 of the bit rate will be described.

In FIG. 1, PCM bit serial data is input to the shift register 1 and the shift register and latch circuit 2, respectively. The shift register 1 has 8 bits (1
Word) configuration, 1 bit serial data
The word is converted to 8-bit word serial data.

The converted word serial data is word-shifted to word latch circuits L1 to L4 having a four-stage cascade structure and sequentially latched for each word.
The final stage latch circuit L4 has a 7-bit configuration. When the bits latched in the word latch circuits L1 to L4 are b1, b2, b3, ... In order from the first bit of the latch circuit L4 as shown in FIG. 2, the final bit of the final stage latch circuit L1 is b31. Become.

In the parallel bits b1 to b31 of all of these latch circuits L1 to L4, the pattern (bit combination) in which the frame synchronization pattern appears periodically is b.
1-b24, b2-b25, b3-b26, b4-b2
7, b5-b28, b6-b29, b7-b30, b8
8 sets of b31.

Therefore, in the present invention, in consideration of this uncertainty (eight kinds of uncertainties), eight frame synchronization sections F1 to F8 are provided corresponding to each of these eight sets of patterns. There is. All of these frame synchronization units F1 to F8 have the same configuration. In FIG. 1, only a specific example of the frame synchronization unit F8 is shown, and the conventional frame synchronization unit (coincidence detection unit 3, 3) shown in FIG. It has the same configuration as the error bit number calculation unit 4 and the frame synchronization determination unit 5).

The various timing signals (latch timing signal, word timing signal, frame timing signal) of each of the frame synchronizing sections F1 to F8 are selectively derived by the selector 7 and are output next to the shift register and the latch circuit 2. Is supplied to the stage circuit. The selector 7 selects the timing signals of the frame synchronization units (F1 to F8) in which the frame synchronization pattern is detected by the frame synchronization determination unit 5.

It should be noted that, in FIG. 1, since the upper 8 bits of the frame synchronizing part which detects the frame synchronizing pattern among the eight frame synchronizing parts F1 to F8 indicates one word in which the frame is synchronized, One word may be externally derived in word parallel.

[0019]

As described above, according to the present invention, even if the PCM data is high speed, the processing speed of the synchronization judgment is PC.
Since the bit rate of M data can be set to 1 / n, a CMOS element can be used without using a high-speed and expensive element such as an ECL element, thereby reducing development cost, power consumption, and Has the effect of increasing the density.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a part of details of the embodiment of the present invention.

FIG. 3 is a block diagram of a conventional frame synchronization detection device.

[Explanation of symbols]

 1 shift register 2 shift register and latch circuit 3 coincidence detection unit 4 error bit number calculation unit 5 frame synchronization determination unit 7 selectors L1 to L4 latch circuits F1 to F8 frame synchronization unit

Claims (2)

[Claims] 1. A frame synchronization detecting device for monitoring frame information transmitted bit serially and detecting a frame synchronization pattern included in the frame information, wherein bit serial input is 1 word n bits (n is an integer of 2 or more). ), A word-serial conversion means for converting the word-serial signal to a word-serial signal, a plurality of word latch means for sequentially latching the word-serial signal in word units, and the number of bits of the frame synchronization pattern among the parallel output bits of the latch means. And n comparing means for respectively comparing n different bit combination patterns with the same number of bits as the reference frame synchronization pattern, and the frame synchronization is detected by these n comparison results. And frame synchronization detection device. 2. The frame synchronization detection device according to claim 1, wherein the word-serial conversion means has an n-bit shift register configuration.