JPH03131032A - Semiconductor device - Google Patents

Abstract

PURPOSE:To supply a fine multifunctional semiconductor device stably without varying a design rule by retreating the line width of a conductive film composed of Al or an alloy thereof more than that of a conductive film at least an upper layer in a wiring shape having laminated structure, in which the upper section or upper and lower sections of the conductive film consisting of Al or the alloy thereof are held by a different kind of conductive films. CONSTITUTION:A cap metal 14, side faces of which are formed approximately vertically to a photo-resist and which is made up of TiN, and a first wiring composed of an Al alloy 13 are shaped, and the Al alloy 13 is side-etched on one side only of the side faces of the Al alloy 13. A silicon oxide film is grown as a first inter-layer insulating film 16, a silicon oxide film is further grown, and formed as a second inter- layer insulating film 17, and the inter-layer insulating film 17 is etched back in order to flatten the inter-layer insulating film of the stepped section of the first wiring. A coated glass film 18 is applied, the whole is annealed, a through-hole is bored through photoetching, an Al alloy 19 as a second wiring and a TiN cap metal 20 are laminated, etching is conducted, and a passivation film is deposited and a pad section for leading out an external electrode is bored. Accordingly, a first wiring space is spread effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device having multilayer wiring, particularly to a wiring structure and its shape.

[Prior art] The wiring in conventional semiconductor devices is generally a single layer of alloy thin film containing Si, Cu, etc. in A1, but in order to achieve fine integration and improve reliability, the wiring structure has been changed to a fourth layer. As shown in the figure, for example, after forming a contact hole to an impurity layer etc. in a field insulating film 12 on a semiconductor substrate 11 on which a semiconductor element is formed, an A1 alloy 13 having a thickness of about 0.5 to 1.0 μm is sputtered. Further, as a cap metal 14 for preventing Al hillocks and halation in the photolithography process, a laminated structure is used in which a conductive film such as TiN is deposited to a thickness of about 0.05 μm. These laminated films are etched by reactive ion etching (RIE) using a halogen gas such as Cl x or BCl using the photoresist 15 as a mask.
Simultaneous patterning is carried out using a dry etcher such as an electron cyclotron resonance etcher (ECR) to form the first wiring (Fig. 4(a)). Next, an interlayer insulating film is formed. The SiH+-0□-based silicon oxide film has large cusping and is not suitable for use as an interlayer insulating film for fine rules.
(OC-Hs) 4] and 02 are plasma-reacted to grow a silicon oxide film with no cusping of about 0.6 μm.In order to fill the space, TEO5 and Ol are thermally reacted to grow a silicon oxide film with good coverage of about 0.6 μm. After growing to a thickness of .4 μm to form the second glabellar insulating film 17 (FIG. 4(b)),
RIE to flatten the insulating film between the eyebrows at the first interconnect step.
After etching back about 0.45 μm with etching etc. (Fig. 4 (
c)) Next, a coated glass film 18 is applied and annealed, a through hole is opened in a photolithography process, and an A1 alloy 19 and a TiN cap metal 20, which will become the second wiring, are laminated (Fig. 4). (d)).

[Problems to be Solved by the Invention] However, in the prior art, the cross-sectional structure after dry etching the A1 alloy 13 and the cap metal 14, which form the first wiring, is almost vertical. , second
The silicon oxide film made by reacting TE01 and TE03 used as the glabellar insulating film 17 causes cusping in a vertical space of about 0.4 μm or less, so if it is laminated on the first interlayer insulating film 16, 0.8 to 1.2 μ of 1 wiring
A void 21 of the second interlayer insulating film 17 is formed in a specific space of m.
This formed a deep groove close to a reverse taper due to etchback, and when the coated glass 18, which was intended to promote flattening, was spin-coded, liquid pools and bubbles 22 were formed, which caused cracks in the glabellar insulating film due to annealing, etc. .

However, the present invention solves these problems, effectively expanding the space of the wiring cross-sectional structure of semiconductor devices, ensuring stable supply of micro multifunctional semiconductor devices without changing design rules, and improving electrical characteristics. The purpose is to improve quality associated with reliability and reliability.

[Means to solve the problem]

In the semiconductor device of the present invention, in a wiring shape having a laminated structure in which a conductive film made of Al or its alloy is sandwiched between different types of conductive films on the upper and lower sides, Al or its alloy The conductive film is characterized by a receding line width.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to FIG.

When applied to multilayer wiring of a submicron rule Si gate CMO3 semiconductor device 1, a semiconductor substrate ll made of Si on which semiconductor elements such as transistors and resistors are formed.
Field insulation by selective thermal oxidation or vapor phase growth method 11
A contact hole for taking out an electrode from the impurity layer etc. is made through the cap T 12, and an A1 alloy 13 containing approximately 0.1 to 0.5% Cu is formed to a thickness of about 0.6 μm.
Sputtering iN14 to a thickness of about 0.05 μm and patterning with photoresist to a thickness of about 15 mm.

When anisotropic dry etching is performed using ECR containing C1a and BC1s gases of rr, the TiN cap metal 14 and A1 whose side surfaces are almost perpendicular to the photoresist are formed.
A first wiring made of alloy 13 is formed. Subsequently, by exposing the A1 alloy 13 to an organic alkali containing a 1 to 8% aqueous solution of tetramethylammonium hydroxide for 30 to 60 seconds, only one side of the A1 alloy 13 is etched by O, 1 to 0.2 μm μm (FIG. 1(a)). After that, the photoresist is peeled off, but this wet etching can be carried out after the photoresist is peeled off.A zero-order glabellar insulating film is formed.
A silicon oxide film with no cusping was grown to a thickness of approximately 0.65 μm by plasma reaction of TE01 and O3 at 0°C, and further TE
After thermally reacting 01 and 0, a silicon oxide film with good coverage is grown to a thickness of about 0.4 μm and used as the second glabellar insulating film 17 (Fig. 1(b)). In order to flatten the film, it is etched back by about 0.45 μm using RIE (Fig. 1 (C)), and then a coated glass film 18 is applied, and after annealing at about 400° C., through holes are made by photo etching. , A1 alloy 19 and Ti which become the second wiring
An N cap metal 20 was laminated (FIG. 1(d)), a passivation film was deposited after etching, and a pad portion for taking out an external electrode was opened.

In the semiconductor device thus constructed, the first wiring space is effectively expanded, and the coverage of the first glabella insulating film 16 at the bottom of the 0.8 to 1.2 μm region is improved, and as a result, the second wiring space is effectively expanded.
The voids in the interlayer insulating film 17 have been eliminated, and problems such as cracks have been improved even when flattening treatments such as etch-back and coated glass have been performed, and the responsiveness of the circuit has been improved by improving reliability and reducing the capacitance between interconnects. I was also able to improve.

Note that a tetramethylammonium hydroxide aqueous solution for side etching A1 alloy 13 was used because it has good etch rate controllability and does not damage the cap metal.
Not only organic alkalis like these, but also KOH, H, PO,
Those using a dilute mixed aqueous solution such as CHI C0OH,
Dry etching is also applicable.

In addition, other embodiments are shown in FIGS. 3 and 4.

In order to improve migration and prevent Al from penetrating into the impurity junction, we applied TiN23 and furthermore Ti24 under it as a barrier metal under the A1 alloy, but as above, reliability and electrical characteristics were Improvements were made. Here, 25 is an impurity layer, and 26 is a Ti silicide layer formed in self-alignment with the impurity layer.

The present invention is applicable not only to the MOSIC of the embodiment but also to bipolar, DMO3, and ICs that combine these.
In addition, as cap metal and barrier metal, W, M
o, high melting point metals such as CO and Cr, their nitrides, and compounds such as silicon materials can also be used. Further, as the main wiring, in addition to Al-CU, pure Al, other metals such as Si, Ti, and Pt, and binary or higher alloys containing silicides and semiconductor materials can also be used.

[Effects of the Invention] As described above, according to the present invention, the lower layer of the laminated wiring in a MOS-LSI etc. has a thinner cross-sectional structure than the upper layer, and the glabella insulating film laminated thereon and the routing of the wiring, This improves flatness, improves electrical characteristics and reliability without changing design rules, and contributes to the supply of more miniaturized and multifunctional semiconductor devices.

[Brief explanation of the drawing]

1(a)-(d), FIG. 2, and FIG. 3 are schematic cross-sectional views showing embodiments of the semiconductor device according to the present invention, respectively. FIGS. 4(a) to 4(d) are schematic cross-sectional views of conventional semiconductor devices, respectively. 11...Semiconductor substrate 12...Field insulating film 13.19...A1 alloy 14.20...Cap metal 15...Photoresist 16... - First interlayer insulating film 17... Second interlayer insulating film 18... Coated glass 21... Void 22... Bubbles 23... ...TiN 24...Ti 25...impurity layer

Claims (1)

[Claims] In a wiring shape having a laminated structure in which a conductive film made of Al or its alloy is sandwiched between different conductive films on top or above and below, the line width of the conductive film made of Al or its alloy is at least wider than the line width of the upper layer conductive film. A semiconductor device characterized by a receding position.