JPH03133674A - Image data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image data processing device that stores and processes input image data in a plurality of lines.

[Conventional technology]

In recent years, recording devices using electrophotographic technology, such as laser beam printers, have become widely used as output devices for computers. These devices have many advantages such as high image quality and low noise, and have contributed to the rapid expansion of the desktop publishing (DTP) field, especially in terms of high image quality.

As shown in FIG. 6, the laser beam printer 200 includes a printer controller 10 and a printer engine section 20.
It consists of The printer controller 10 decomposes the code data sent from the host computer 400 based on the application software stored on the floppy disk 300 into dot information, develops it on the bitmap memory, and sends the code data to the printer engine section 2.
Send to 0. The data on the bitmap memory is binary data indicating whether the dot is to be hit or not. Therefore, when printing an image such as a photograph using a laser beam printer, a widely used method for obtaining gradations has been to convert a multilevel signal into a binary signal using dither processing or the like on the host computer 400 side. Ta.

On the other hand, in recent years, a pulse width modulation (PWM) method has been proposed and realized as a technology that achieves both resolution and halftone reproducibility at a higher level.

Recently, various high-quality image processing techniques have been proposed from both binary processing and multi-value processing. among them,
A particularly noteworthy technique is a method that focuses on a certain pixel, such as smoothing processing in binary processing, and performs processing based on the states of pixels around that pixel.

In this method, in order to determine the gradation of a pixel of interest, it is necessary to refer to multivalued data or binary data of surrounding pixels. FIG. 7 is a block diagram showing the configuration of the printer engine section 20 related to such a method.

In FIG. 7, the printer controller 1° receives a horizontal synchronization signal HS periodically generated by the laser unit 103.
Upon receiving YNC, in synchronization with transfer lock VCLK, one line of image data (e.g., 8 bits), that is, 6-bit multivalued data VDO to VD5 (hereinafter, the reference symbol rVDJ will be used when referring to them collectively); The binary data VIDEO1 and the multi-value binary identification signal 1/T are sent to the printer engine section 2.
Transfer to 0. The memory unit 30 sequentially stores and stores the image data for one line, and when reading it out, the image data for six lines is read out in synchronization with the image clock LCLK generated by the clock generation circuit 26 of the printer engine unit 20. Data is read. At this time, the binary data is processed by the binary processing unit 1.
o.

Then, the multi-value data is sent to the multi-value processing section 101 and the latch circuit 27
After being sent to the synthesis unit 1 and processed,
The 0 synthesis unit 102 sent to the 02 synthesizes image data according to the identification signal I/T input via the latch circuit 27.

The compositing unit 102 performs compositing processing to superimpose an image based on binary data VIDEO obtained by developing characters such as letters, and an image having halftones based on multi-value data VD.

The output of the combining section 102 is sent to the laser unit 103, which modulates the laser beam. This laser beam scans a photosensitive drum (not shown) to form an electrostatic latent image. This latent image is made visible by toner development, and then transferred and fixed onto recording paper. The recording operation in the laser beam printer 200 is performed in this manner.

In the printer engine section 20, the transfer lock VCLK from the printer controller 10 and the image clock LCLKn of the printer engine section 2o are not necessarily the same considering the compatibility between the printer controller 1o and the printer engine section 20. There's no need.

FIGS. 8 and 9 show a circuit diagram and a time chart of the memory section 3o.

In FIG. 8, 8-bit image data sent from a printer controller (not shown) is manually input to three-state buffers 31-37.

In FIG. 9, when the image data of line 1 is input, only the 3-state buffer 31 is enabled (FIG. 9 (1)), and the input image data is stored in the memory 41.
is output as is to the data bus. The remaining three-state buffers 32 to 37 are in a disabled state, and their output terminals are in high impedance. In addition, only memory 41 is in the write mode, and its address is specified by the 9th figure because the selector 51 has selected 8-bit power, and the write operation to the memory 41 is performed sequentially at the timing of this transfer lock VCLK. is performed (for example,
When the resolution is 300 dpi and the paper size is A4, the number of dots for one line in the main scan is approximately 2400, so a 12-bit (2" = 4096) address line is required as shown in FIG. -47 are in read mode, and selectors 52-57 select input to, so the addresses of memories 42-47 are based on the image clock LC.
Read address counter 3 counted up with LK
9, and read operations from the memories 42 to 47 are performed at the timing of the image clock LCLK. In addition, "W" in Fig. 9 (2) to Fig. 9 (8)
represents write mode, and "R" represents read mode.

When the horizontal synchronization signal H3YNC is input and the second line of image data is sent, the two address counters 38 and 39 are activated by the horizontal synchronization signal H3YNC.
Both are cleared, and the device control circuit 40
Only the buffer 32 is set to the write mode, only the buffer 32 is set to the enable pull state, and only the selector 52 is set to the B input selection, and the image data that has been sent is written to the memory 42. At this time, the remaining buffers 31.33-37, memory 41.
43 to 47 and selectors 51 and 51 and 53 to 57 are in a disabled state, a read state, and an A input selection, respectively, and data in the memories 41 and 43 to 47 are sequentially read out at the timing of the image clock LCLK. In this way, a state in which only one of the seven memories 41 to 47 is in the write mode and the rest are in the read mode is repeated every seven lines.

In other words, the image data of each line is stored in seven memories 41 to 4.
At this time, image data for six lines before that line is read out from the other six memories.

The multiplexer 48 selects one of the seven memories 41 to 47,
The image data from the six memories in read mode are selected and rearranged in chronological order ((10) in FIG. 9).
When the write mode is sequentially switched from 1 to the memory 47, for example, if the memory 45 is in the write mode,
The oldest line of image data to be read is Meso4.
The image data of the newest line is stored in the memory 44. In this case, multiplexer 48
outputs the image data in the memory 46 to the data line Jlf, and outputs the image data in the memory 44 to the data line Jlf. That is, the multiplexer 48 has 6 to be derived.
The image data for the lines are rearranged so that the image data for the oldest line to the image data for the newest line are derived chronologically into data lines ft, ~JLt.

In this way, the multiplexer 48 outputs six lines of image data. At this time, the image data of each line is output in 8-bit serial format, but when referring to the image data of 6×6 pixels around the pixel of interest, for example, the multi-value processing unit 101, the binary processing unit 100, etc. A shift register having six cells is provided for each bit, and the gradation of the pixel of interest is determined by referring to the data in this shift register. FIG. 9 (10) shows the line where actual printing is performed.

(Problem to be solved by the present invention) However,
In the conventional example, data is written to the seven memories once every seven times, and since the write clock and read clock are different, the addressing timing is also different. Since all memories 41 to 47 must be addressed at both addressing timings, it is not possible to share the address bus.
A huge number of address lines, 7×12=84, are required. Therefore, the circuit board becomes larger,
There was a problem in that the overall size of the device was increased.

Also, output from each memory x8 = 56 from tree 8x8 =
This requires the tedious process of selecting 48 videos and rearranging them in chronological order. Therefore, many multi-bit selectors are required around the memory, and the circuit configuration becomes difficult. ! The problem is that it becomes cluttered.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image data processing device that solves the above technical problems, simplifies the circuit configuration, and is advantageous for downsizing the entire device.

[Means to solve the problem]

In order to achieve the above object, an image data processing device according to the present invention is an image data processing device that inputs image data for each line and outputs multiple lines of image data.
first and second storage means capable of storing one line of image data; a first switching means for switching and writing input image data into either the first or second storage means; a second switching means for switching and reading image data from the other of the first or second storage means; a third storage means for storing the image data from the second switching means; and control means for causing the first and second switching means to perform a switching operation each time a line of image data is input, and outputting image data from the second switching means and the third storage means. It is characterized by the following.

The image data processing device according to the present invention also provides a first address signal for a write operation of the first or second storage means, and a second address signal for a read operation of the first or second storage means. and third switching means for switching and deriving the first address signal to the first or second storage means in which a write operation is performed and the second address signal to one in which a read operation is performed. It is characterized by containing.

(Function) According to the present invention, input image data is written in either the first or second storage means, and the switching is performed alternately for each line by the first switching means. Further, the second switching means selects and outputs the image data of the first or second storage means on which the writing operation has not been performed. The image data derived from the second switching means is output to the outside and is also written into the third memory. At this time, the image data of the previous line stored in the third memory is output to the outside. In this way, multiple lines of image data are output from the image data processing device.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a memory section 30a according to an embodiment of the present invention. This memory section 30a is used in place of the memory section 30 in FIG. 7 described above, so the overall explanation will be omitted here and only the memory section 30a will be explained.

In the first section, the memories 60 and 61 can store, for example, one line of image data with a resolution of 300 dpi, and when one is in the write mode, the other is in the read mode, and the HSYNC signal is sent to the device control circuit 40.
The mode changes each time you enter. In addition, the selector 77
．． Reference numerals 78 correspond to the memories 60 and 61, and when the corresponding memories are in the write mode, the output of the write address counter 58 is selected, and when the corresponding memories are in the read mode, the output of the read address counter 59 is selected. This write address counter 58 counts transfer lock VCLK from the video controller 10. Further, the image clock LCLK is obtained by dividing the reference clock BCLK generated by the clock generator 69 by eight by the frequency divider 68, and the read address counter 59 counts this image clock LCLK.

Note that the image clock LCLK is also used as a latch clock for the latch circuit 27.

The MPX 70 outputs 8-bit image data from the printer controller 10 to one of the memories 60 and 61 that is set to read mode. At this time, the output end to the data line connected to the memory in write mode becomes high impedance. Further, the selector 79 selectively reads image data from the memory in the write mode among the memories 60 and 61 and outputs it to the three-state latch buffer 71.

Six 3-state latch buffers 71-76 are connected in series, and memories 62-66 are connected between each 3-state latch buffer. As a result, for example, the image data from the 3-state latch buffer 71 is output to the processing section and the like, as well as to the memory 62. Address lines from read address counter 59 are commonly connected to memories 62-66, and operations similar to those described above are performed simultaneously in other three-state latch buffers 72 and memories 63-66. Such processing operations are performed based on control signals output to each circuit from a timing signal generator 67, which will be described later.

Next, processing operations related to control of the device control circuit 40 will be explained with reference to the flowchart of FIG.

When the H3YNC signal is input in step S1, the 8-bit image data VDO is transferred in synchronization with the transfer lock VCLK.
will be transferred. Then, the device control circuit 40
clears both address counters 58 and 59 in step S2, and clears selectors 77 to 79 and MPX7 in step S3.
0 to the A side, for example. If the memory 60 is in the read mode at this time, the input of the H3YNC signal causes it to switch to the write mode in response to the switch to the A side (step S4).

Since the selector 77 has been switched to the A side, it selects the input from the write address counter 58 and sends it to the address terminal of the memory 60. At the same time, since the MPX 70 has selected the A output, it sends the image data to the data terminal of the memory 60. In this way, the image data VD is sequentially written into the memory 60 using the transfer lock VCLK.

Further, in step S4, the memory 61 changes from the write mode to the read mode in response to the switching to the A side by the H3YNC signal. The selector 78 also selects the input from the read address counter 59 and sends it to the address terminal of the memory 61. Read address counter 5
9 is supplied with an image clock LCLK, and the image data in the memory 61 (the image data of the previous line written in the memory 60 in the above-described operation) is sequentially read out in synchronization with the image clock LCLK. At the same time, the selector 79 selects the A input, and sends the image data read from the memory 61 to the three-state latch buffer 71 (step S5).

FIG. 3 is a detailed circuit diagram around the timing signal generator 67. The timing signal generator 67 includes, for example, a shift register 85 having eight cells and logic circuits 81 to 8.
3. The aforementioned reference clock BCLK is input to the input terminal CK of the shift register 85, and a high level voltage is applied to the input terminal. Further, the output terminal H is connected to the input terminal CLR.

As mentioned above, the image clock LCLK is generated by dividing the reference clock BCLK by 8, but since this timing signal generator 67 uses the reference clock BCLK as the operating clock signal, the image clock LCLK is divided by 8 during one period of the image clock CLCK. can be performed in two steps.

The 3-state latch buffer 71 is composed of a latch circuit 71a and a buffer circuit 71b as shown in FIG. 3 (only the configuration corresponding to 1 bit is shown in FIG. 3). .

Next, the operation of the timing signal generator 67 will be explained with reference to the time chart of FIG. Note that in the following description, the data of the n-th pixel is referred to as data(n), and the address where the data is stored is referred to as adr(n).

When the first clock is input after the image clock CLCK shown in FIG. 4 (1) becomes low level (time t1)
, the enable signal oC of the 3-state latch buffers 71 to 76 (hereinafter, only the 3-state latch buffer 71 will be referred to) becomes FALSE ((9) in FIG. 4), the buffer circuit 71a becomes high impedance, and no output is generated. The previous data data (n-1) stopped, and nothing is input to the data bus of the memory 62 (FIG. 4(io)).

When the second clock is input (time t2), the MOE signal becomes TRUE (Fig. 4 (5)), and the memory 60 or memory 61 enters the read state (Fig. 4 (12)).
, data dat stored at address adr(n)
a(n) is output on the data bus.

When the third clock enters (time t3), the data data(n) that has been output on the data bus is latched inside the 3-state latch buffer 71 (Fig.
)). However, since the output enable signal oC shown in FIG. 4(9) remains FALSE, it is not output to the outside of the three-state latch buffer 71. Therefore,
Bus collisions will not occur.

When the fourth clock enters (time t4), the memory 62
The output enable signal MOE becomes FALSE, and the memory 62 becomes a floating state.

When the fifth clock is input (time t5), the output enable signal QC of the 3-state latch buffer 71 becomes TRU.
E, the latched data data (n) is output and sent to the memory 62, but the memory 62
Write enable signal MWE83 shown in Figure (11)
is FALSE, so it is not written.

When the sixth clock enters (time 6), the memory 62
The write enable signal MWE becomes TRUE, and data (n) is written into the memory 62.

When the seventh clock is input, the write enable signal MWE becomes FALSE, and the write operation is completed.

'When the M8th clock is input, the shift register 85 is cleared and the address changes from adr (n) to ad
r(n+1), and a series of operations regarding the pixel data is completed. Such operations are performed similarly and simultaneously for the three-state latch buffers 72-76 and the memories 63-66.

In this way, data in the memory 62 is written to the memory 63 during one cycle of the image clock LCLK,
Data in memory 60 or memory 61 is written to memory 62.

By repeating this operation, the memories 60 to 66 always store image data for 6 lines in the main scanning direction, and at the same time, the processing circuit always stores data arranged in chronological order, that is,
The newest line of image data is sent from the 3-state latch buffer 71, and the image data is sent to the 3-state latch buffer 76.
The image data of the oldest line is sent out.

(Other Embodiments) FIG. 5 shows the memory section 30b of Akira Himi's second embodiment. In the first embodiment, both the printer engine section 20 and the printer controller 10 are 300 dpi processing systems, and in order to maintain compatibility between the printer controller and the blink engine, a transfer lock VCLK and an image clock LCL are used.
K was considered separately, but in this embodiment, the printer controller 10 sends 300 dpi or 600 dpi data, and the printer engine unit 20 sends 800 dpi data.
This assumes that it will be processed in

In FIG. 5, the same reference numerals are used for parts corresponding to those in FIG. 1.

First, consider a case where 600 dpi data is sent. The printer controller 10 uses a command signal CMD to notify that the data to be sent is 600 dpi data. Then, the synchronization signal generator 96 outputs the BD signal sent from the laser unit 103 as the horizontal synchronization signal H3YNC. Further, the frequency divider 68 divides the reference clock BCLK by eight and outputs the image clock LCLK. Other than the fact that the memory address lines have become 13-tree and the reference clock BCLK has changed four times,
The basic operation is the same as the first embodiment.

Next, consider a case where 300 dpi data is sent.

Since the printer engine 20 side is a 600 dpi processing system, data conversion is required. Therefore, consider reading data from the memory 60 or the memory 61 twice while 300 dpi data is being sent.

The printer controller 10 uses a command signal CMD to notify that the data to be sent is 300 dpi.

Then, the synchronization signal generator 96 divides the frequency of the BD scratch signal by two and outputs the horizontal synchronization signal HSYNC. Then, the printer controller 10 receives this horizontal synchronization signal H5YNC and sends 300 dpi data during that time. On the other hand, the device control circuit 40 sets the write address counter 58 to H3Y.
The read address counter 59 is cleared from the BD scratch signal by the NC signal.

Also, memory 60, 61, selector 77, 78, MPX
70 is switched by the HSYNC signal. Therefore, for example, while data is being written to the memory 60, data is being read from the memory 61. Thereafter, when the BD signal 97 is input, the read address counter 59 is cleared and the data is read again from the first address. However, since the write address counter 58 is not cleared, writing continues.

In this way, by reading out the image twice from the memory 61, the image becomes a pseudo 600 dpi in the sub-scanning direction, and is sequentially written into the memories 62 to 67.

In addition, a clock with a frequency obtained by dividing the reference clock BCLK by 4 with a quarter period of 98, that is, a clock with a frequency twice that of the image clock LCLK, is sent to the processing system, and a latch operation is performed at this frequency. Both scanning and scanning are 60
The data will be 0 dpi.

In the embodiment described above, the pixel density of data is 300d.
I gave an example of the case of pi and 600 dpi, but 4
The resolution may be 00 dpi or 800 dpi, and although the number of memories is seven, this number may be any number.

Further, although the description has been made using a laser printer, the present invention is not limited to this.

〔Effect of the invention〕

By configuring as described above, the number of signal lines on the board can be reduced, so the circuit board can be made smaller and the entire device can be made smaller.

You can also save on peripheral devices,
The circuit configuration is simplified.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention, and is a block diagram showing the configuration of a memory section 30a which is an image data processing device. FIG. 2 is a flowchart for explaining the control operation of the device control circuit 40 of the memory section 30a. , FIG. 3 is a detailed circuit diagram around the timing signal generator 67 of the memory section 30a, FIG. 4 is an operation timing chart of the timing signal generator 67, and FIG. 5 is a diagram of the memory section 30b of another embodiment of the present invention. 6 is a schematic block diagram showing the peripheral structure of a general laser beam printer 200 in the prior art. FIG. 7 is a block diagram showing the structure of the printer engine section 20 of the laser beam printer 200. 8 is a detailed circuit diagram of the memory section 30 of the printer engine section 20, and FIG. 9 is an operation timing chart of the memory section 30. 30a...Memory unit (image data processing device) 40...
- Device control circuit (control means) 60...Memory (first storage means) 61...Memory (second storage means) 62...Memory (third storage means) 67...Timing signal Generator 69...Clock generator

Claims (2)

[Claims] (1) An image data processing device that inputs image data for each line and outputs multiple lines of image data, which comprises first and second storage means capable of storing one line of image data, and the input image data. A first switching means that switches to write image data into either the first or second storage means; and a second switching means that switches and reads image data from the other of the first or second storage means. a switching means; a third storage means for storing the image data from the second switching means; and a switching operation is performed on the first and second switching means each time one line of image data is input. An image data processing device comprising: a control means for outputting image data from the second switching means and the third storage means. (2) inputting a first address signal for a write operation of the first or second storage means and a second address signal for a read operation of the first or second storage means;
Alternatively, the second storage means may include a third switching means for switching and deriving the first address signal to the one in which a write operation is performed and the second address signal to one in which a read operation is performed. The image data processing apparatus according to claim 1.