JPH031396A - Data writing and erasing method for semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase reloadable time without increasing the number of manufacture processes or the size of a cell by separating a current path for writing and erasing into a source area and a drain area. CONSTITUTION:A source area 23 and a drain area 22, in which the concentration of impurity is almost equal, are formed in a substrate and a floating gate 25 and a control gate 27 are formed through insulating films 24 and 26 on the substrate. When data are written, an electric charge is injected to the floating gate 27 near the drain area 22 and the data are erased, the electric charge is neutralized in the floating gate 27 near the source area 23. Then, each current path is separated for the time of writing and the time of erasing and the insulating films 24 and 26 under the floating gate 27 are suppressed to be degraded. Thus, since the concentration of the impurity is almost equal in the source area 23 and drain area 22, the number of the manufacture processes can be decreased and the size of the cell can be reduced. Then, the reloadable time can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for writing and erasing data in a semiconductor memory device, and in particular to an electrically erasable EPROM (Electric Memory Device).
Cally Programmable Read 0
The present invention relates to a data writing and erasing method for nly Memory.

(Prior art) Conventionally, data can be written to an EPROM having a floating gate electrically, but data can be erased using ultraviolet rays for about 100 ms.
This is done by irradiating through the glass window of the package for 1 minute. However, this type of EPROM has drawbacks such as the need for an ultraviolet irradiator, the risk of blindness due to ultraviolet rays, and the cost of a package with a glass window compared to a regular package without a window. Therefore, electrically erasable EPROMs (usually all bits are erased at once and are called flash EEPROMs, etc.) are disclosed in U.S. Pat. This method has been proposed in Publication No. 63-249°375 (Document 2).

FIG. 2 is a schematic cross-sectional view of the conventional EPROM cell described in Document 1.

This EPROM consists of a p-type silicon substrate (Si substrate) 1
In the main surface of the Si substrate 1, there is a drain region 2 made of an n+ diffusion layer, and a DDD (Double Diffused Dr.
ain (double diffused drain) structure is formed. Furthermore, a floating gate 5 is formed on the Si substrate 1 with an insulating film 4 interposed therebetween, and a control gate 7 is formed on the floating gate 5 with an inter-glabellar insulating film 6 interposed therebetween.

In this EPROM, the high control gate potential VG
is applied to the control gate 7, a high drain potential VD is applied to the drain region 2, and a saturated channel current is caused to flow between the drain region 2 and the source region 3, thereby increasing the threshold voltage VT of the memory cell and transmitting data. is written.

In the case of erasing data, a high source potential VS is applied to the source region 3 asymmetric to the drain region 2, and a Fowler-Nordheim tunnel flows through the insulating film 4a in the overlapped portion of the source region 3 and the floating gate 5. Data is erased using electric current. That is, the source region 3 is made of DDD m structure, and the source region 3 and the Si substrate 1 are
By weakening the electric field between the two, the generation of avalanche current is suppressed, and data is erased using Fowler-Nordheim tunneling current.

FIG. 3 is a schematic cross-sectional view of a conventional EPROM cell described in Document 2.

This (7) EPROM has a p-type Si substrate 11, and a drain region 12 and a source region 13 of the same structure made of an n+ diffusion layer are formed in the main surface of the Si substrate 11, and further, A gate oxide film 14, a floating gate 15, a silicon oxide film 16, and a control gate 17 are formed in this order on 11 in a laminated state.

When writing data in this EPROM, for example, the control gate potential VG is set to 13 V, the source potential VS and the substrate potential VB are set to OV, and a pulse of drain potential VD = 8 V is applied to the drain region 12 for 0.1 m5ec. As a result, the threshold voltage VT of the memory cell increases from 1.8V to approximately 6V, and data is written.

When erasing data, a high potential is applied to the drain region 12, and avalanche current is actively used to erase data. That is, the switch 18 is closed, the switch 19 is kept open, and the control gate potential V is applied to this memory cell.
Apply G=substrate potential VB=Ov and source potential VS=2V. Next, the switch 19 is closed and the drain potential VD
A pulse of =14■ is applied to the drain region 12. As a result, the threshold voltage VT of the memory cell changes from, for example, 6.6■ to 2.0■, and data is erased.

FIG. 4 shows changes in the threshold voltage VT of the memory cell shown in FIG. 3 when writing and erasing are repeated in the above-described method.

FIG. 4 is a characteristic diagram of the threshold voltage with respect to the number of repetitions of writing and erasing. In this figure, VTo is the initial value voltage after UV irradiation, and the writing time for the memory cell is 1
011m5ec per time, erasing time is 100m5 per time
It is ec. As is clear from this figure, as the number of repetitions of writing and erasing increases, the difference between the threshold voltage after writing and the threshold voltage after erasing (so-called threshold window) becomes narrower.

(Problem to be solved by the invention) However, in the above data writing and erasing method,
The following issues were encountered.

(1) In the method shown in Fig. 2, the source region 3 is made into a DDD structure and the electric field between the source region 3 and the Si substrate 1 is weakened to suppress the generation of avalanche current. , the insulating film 4 is erased by repeating data writing and erasing.
There is little deterioration of a. Therefore, writing and erasing can be expected over 1000 times. However, since only the source region 3 side has a DDD structure, the photolithography process, ion implantation process, etc. are increased in order to fabricate the DDD structure, which has the disadvantage of increasing the cost due to the increase in the number of manufacturing processes. Ta.

Moreover, since the source region 3 has a DDD structure, the source region 3 also expands in the lateral direction. The channel length between the drain region 2 and source region 3 is a factor that determines the characteristics of the memory cell, and if you want to obtain a constant channel length, D
The gate length of the memory cell must be increased by the amount of lateral expansion due to the DD structure, which has the drawback of increasing the cell size by, for example, about 0.3 μm per memory cell.

(2) In the method shown in FIG. 3, since data is erased by actively utilizing avalanche current, the drain region 12
and the source region 13 can have the same structure. Therefore, the second
Since there is no need to employ a special structure such as the DDD structure shown in the figure, the disadvantages of the increase in the number of manufacturing steps and the increase in cell size described in (1) can be eliminated.

However, during data writing, negative charge is injected into the floating gate 15 near the drain region 12.
During erasing, the negative charges in the floating gate 15 are similarly neutralized near the drain region 12. In this way, the current paths during programming and erasing are all connected to the drain region 1.
2, the gate oxide film 14 near the drain region 12 is likely to deteriorate. Therefore, depending on the configuration of the data successive output circuit, as shown in FIG.
The drawback is that the number of times it can be rewritten is limited to several thousand to several hundred times.

As mentioned above, in the conventional data writing and erasing method,
It has been difficult to obtain a data writing and erasing method that requires a small number of manufacturing steps, a small cell size, and a large number of rewrites.

The present invention solves the problems of the prior art in that it is difficult to obtain a method for writing and erasing data with a small number of manufacturing steps, a small cell size, and a large number of rewrites. The present invention provides a method for writing and erasing data.

Means for Solving the Problems) In order to solve the above problems, the first invention provides a method in which a source region and a drain region having substantially equal impurity concentrations are formed in a substrate, and a source region and a drain region having substantially equal impurity concentrations are formed on the substrate through an insulating film. The following measures are taken in a data writing and erasing method for a semiconductor memory device in which a MOS transistor in which a floating gate and a control gate are formed is used as a memory unit.

That is, data is written by setting the absolute value of the drain potential applied to the drain region to a larger value than the absolute value of the source potential applied to the source region, and The drain region is set to a potential state that can prevent reverse current, and a predetermined potential that can prevent channel formation between the source region and the drain region is applied to the control gate, and the drain potential is changed. Data is erased by applying the source potential having an absolute value larger than the absolute value to the source region.

In a second invention, in the first invention, the absolute value of the source potential during data erasing is set to be larger than the absolute value of the drain potential during data writing.

(Function) According to the first invention, since the data writing and erasing method for a semiconductor memory device is configured as described above, the absolute value of the drain potential is set to a larger value than the absolute value of the source potential, and data is written. When writing, a large current flows between the drain region and the source region, and some of the hot electrons generated by impact ionization reach the control gate along the electric field in the direction of the control gate. At this time, since the control gate is surrounded by an insulating film and is in an electrically floating state, the hot electrons are stored in the floating gate, and the threshold voltage of the memory cell increases, allowing data to be written.

When erasing data, if the drain region is set to a potential state that can prevent reverse current between the drain region and the substrate, current flow from the drain region to the substrate is blocked. When a predetermined potential that can prevent channel formation between the source region and the drain region is applied to the control gate, the flow of channel current between the source region and the drain region is prevented. When a source potential higher than the drain potential is applied to the source region, an avalanche current is generated, but the current flows from the source region to the drain region without reaching breakdown, and the charge accumulated in the floating gate is removed and the memory The threshold voltage of the cell is lowered and data is erased.

In this way, when writing data, charge is injected into the floating gate near the drain region, and when erasing data, charge is neutralized in the floating gate near the source region. Each current path is separated at the time, deterioration of the insulating film under the floating gate is suppressed, and the number of data rewrites is increased.

Furthermore, since the source region and the drain region have substantially the same impurity concentration, the number of manufacturing steps and the cell size can be reduced.

In the second invention, when erasing data, if the source potential is set higher than the drain potential, data of only the target memory cell can be accurately erased, thereby preventing erasure of data of other memory cells. There is work.

Therefore, the above problem can be solved.

(Embodiment) FIGS. 1(a), (b), and (c) show an embodiment of the present invention, and are schematic cross-sectional views of an EPROM cell constituted by an N-channel MOS transistor.

A large number of these EPROM cells are formed in an array on, for example, a P-type Si substrate 21, and a drain region 2 with a depth XJ of about 0.25 μm is formed in the main surface of the Si substrate 21.
2 and source region 23 are formed at the same time. The drain region 22 and source region 23 are formed of N+ diffusion layers having the same impurity concentration. drain region 22
On the source region 23, a gate insulating film 24 made of, for example, a silicon oxide film (SiO2 film) with a thickness of 3000 μm is formed, and further thereon, a polysilicon film (polycrystalline silicon film) etc. with a thickness of 3000 μm is formed. floating gate 2
5. An insulating film 26 and a control gate 27 made of a polysilicon film or the like having a thickness of 3000 are sequentially formed in a stacked state using a self-line technique or the like.

The insulating film 26 between the floating gate 25 and the control gate 27 is formed of, for example, a SiO□ film with a thickness of 400 mm. Note that this insulating film 26 is made of, for example, a 5i02 film and a silicon nitride film (SiN) instead of the 5iCh film.
It may be formed of a laminated film of. In this way, when the insulating film 26 is formed as a laminated film, the SiN film in the laminated film is SiO
The control gate 2 has a higher dielectric constant than the control gate 2.
5 and the floating gate 27 can be increased.

For example, this EPROM cell has an effective gate length of 0.8μ.
m (gate length 1.2 μm), initial quantity value voltage VT after ultraviolet irradiation when ultraviolet rays are erased. has a characteristic of 1.8■.

In order to write and erase data in such an EPROM cell, for example, the substrate potential VB is held at the ground potential, and a switch 28 is applied to the source region 23 in order to apply a predetermined source potential S to the source region 23. A power source E1 is connected to the drain region 22 through the drain region 22 in order to apply a predetermined drain potential VD to the drain region 22.
A power supply E2 is connected to the switch 29 via a switch 29. Further, a predetermined control gate potential VG is applied to the control gate 27.

Next, Figures 1 (a), (b), (c), Figures 5 and 6
How to write data to an EPROM cell (1) with reference to the diagram
) and data deletion method (2) will be explained.
FIG. 5 is a characteristic diagram of the threshold voltage VT with respect to the erasing time in FIG. 1, in which VT is the initial amount voltage after irradiation with ultraviolet rays, and ■Ta is the threshold voltage immediately after writing. Further, FIG. 6 is a characteristic diagram of the threshold voltage VT with respect to the number of repetitions of programming and erasing in FIG. 1.

(1) Data writing method When writing data to an EPROM cell, as shown in FIG. 1(a), a control gate potential VG=13V is applied to the control gate 27, and the substrate potential VB is set to OV, and Open switch 28 to switch to source area 2
The source potential of 3 is set to VS-〇■.

In this state, the switch 29 is closed and the drain potential VD
A pulse of =8V is applied to the drain region 22 for 0.1 m5ec. Then, the drain region 22 and the source region 23
During this period, a large current flows, and at that time, some of the hot electrons generated by impact ionization reach the floating gate 25 along the electric field in the direction of the floating gate 25.

At this time, the floating gate 25 is connected to the gate insulating film 24.
Since it is surrounded by an insulating PLA 26 and is in an electrically floating state, the hot electrons are accumulated in its floating gate 25. As a result, the threshold voltage VT of the cell increases from, for example, about 1.8V to about 6V, almost no current flows during reading, and data has been written.

(2> Data erasing method When erasing the written data, as shown in FIG. 1(b), open the switch 28 and close the two switches to control the control gate potential VG = substrate potential VB = OV. While applying voltage to the gate 27, the Si substrate 21
is set to OV, and a drain potential VD=2V is further applied to the drain region 22. As a result, a reverse bias is applied between the drain region 22 and the Si substrate 21, and current flow from the drain region 22 to the Si substrate 21 side is blocked.

Next, as shown in FIG. 1(C), the switch 28 is closed from the state shown in FIG. 1(b), and a pulse of source potential VS=14V is applied to the source region 23.

Here, since the control gate potential VG is OV, generation of channel current between the drain region 22 and the source region 23 is suppressed. Also, source potential VS=1
By applying 4V, the source region 23 and the Si substrate 21 are reverse biased, and an avalanche current is generated, but breakdown does not occur, so a source current of 200 μA or less flows from the source region 23 toward the Si substrate 21. . As a result, the charges accumulated in the floating gate 25 are removed, and data is erased.

The relationship between the pulse application time and the threshold voltage under the voltage application conditions shown in FIGS. 1(b) and 1(c) is shown in FIG.

As shown in FIG. 5, the threshold voltage V immediately after writing
An EPROM cell with T = 6.6V has a voltage of 50ms e
After applying c, the threshold voltage VT=2. It can be seen that the voltage has returned to OV, which is approximately the threshold voltage before writing, and that erasing is about to be saturated there. Here, Fig. 1 (b), (c
Under the bias conditions for erasing data at H;:, an avalanche current flows between the source region 23 and the Si substrate 21, but the current is very small, 200 μA or less, for example, about 100 μA. This is because the drain potential VD is as high as 2■ and no channel current flows between the source region 23 and the drain region 22. Suppose the drain potential VD is set to 0.
If it is set to (2), data can be erased, but breakdown occurs and the source current becomes excessive, which may lead to melting of the wiring or thermal destruction of the EPROM cell.

Therefore, the drain potential VD needs to be biased toward the cell to such an extent that breakdown current does not flow between the source region 23 and the drain region 22.

FIG. 6 shows the dark value voltage characteristics when electrical writing and erasing are repeated for one EPROM cell using the data writing and erasing method described above. In this Figure 6, the writing time is O, 1m5ec per time,
The erasing time is 100 m5ec per time. As is clear from this figure, the number of repetitions is 1000 (writing 50
Even after 0 times and 500 times of erasing), the difference between the threshold voltage VT after writing and the threshold voltage VT after erasing is about 3.5 V, which is much improved compared to the conventional example shown in FIG.

The advantages of this embodiment can be summarized as follows.

(a> When writing data, the drain region 22
A high potential is applied to the source region 23 during data erasing to block current caused by avalanche current, so there is no need to increase the number of manufacturing steps or increase the cell size. The number of rewrites possible can be increased from the conventional several thousand to several hundred times to approximately one thousand times or more.

This is due to the following reasons. That is, during writing and erasing, negative charges are injected into the floating gate 25 near the drain region 22 during writing, and during erasing, negative charges in the floating gate 25 occur near the source region 23. Since the current paths in FIG. This has resulted in a significant increase in the number of rewrites.

(b) Since the source potential VS during data erasing is made larger than the drain potential during data writing, other EP
Erasing of data stored in a ROM cell can be prevented, thereby allowing accurate data writing.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(i) At the time of erasing in FIGS. 1(b) and 1(c), by opening the switch 29 and making the drain region 22 a floating state, charges accumulated in the stray capacitance etc. existing on the side of the drain region 22 are generated. It is also possible to block the current between the source region 23 and the drain region 22 by utilizing this. In this case, the power supply E2 applied to the drain region 22 becomes unnecessary, and the data erasing operation becomes easier.

Furthermore, when erasing data, the control gate potential VG is set to OV in the above embodiment;
Even if G is set to Ov or less, data can be erased almost in the same way as in the above embodiment.

(ii) In the above embodiment, an EPROM cell consisting of an N-channel MOS transistor was explained.
The present invention is also applicable to EPROMs including channel-type MOS transistors. That is, in FIG.
By making the i-substrate 21 N-type, forming the drain region 22 and source region 23 formed in the substrate with a p+ diffusion layer, and reversing the polarity of the power supplies El and E2, the structure shown in FIG. It is possible to write and erase data in substantially the same manner as in the above embodiment by performing substantially the same operations.

(rir) The Si substrate 21 may be made of another material, and the cross-sectional structure of the EPROM cell may be modified to a structure other than that shown in FIG.

(iv) In FIG. 1, the drain region 22 and the source region 23 are mutually compatible, and the source side and drain side can only be identified when they are connected to another circuit, so the above data writing takes these into consideration. and the operating procedure of the erasing method may be selected as appropriate.

(Effects of the Invention) As described above in detail, according to the first invention, by dividing the side to which a high potential is applied into the source region side and the drain region side during data writing and data erasing, That is, since the current paths for writing and erasing are separated into the source region and the drain region, deterioration of the insulating film under the floating gate can be significantly reduced. As a result, the number of rewrites can be significantly increased without increasing the number of manufacturing steps or cell size.

Furthermore, in the second invention, since the absolute value of the source potential during data erasing is made larger than the absolute value of the drain potential during data writing, erasing of data in other memory cells is prevented and the desired memory Accurate data can be written to cells.

[Brief explanation of the drawing]

1(a>, (b), and (c) are schematic sectional views of an EPROM cell showing an embodiment of the present invention; FIGS. 2 and 3 are schematic sectional views of a conventional EPROM cell; The figure shows the number of write/erase repetitions vs. threshold voltage characteristic in Figure 3, Figure 5 shows the erase time vs. threshold voltage characteristic in Figure 1, and Figure 6 shows the number of write/erase repetitions vs. threshold voltage characteristic in Figure 1. 21... Si substrate, 22... Drain region, 23... Source region, 24...
Gate insulating film, 25... Control gate,
26... Insulating film, 27... Control gate, 28.29... Switch, VB...
...Substrate potential, VD...Drain potential, VG
...Control gate potential, VS...
・Source potential.

Claims (1)

[Claims] 1) A MOS transistor in which a source region and a drain region having substantially equal impurity concentrations are formed in a substrate, and a floating gate and a control gate are formed on the substrate through an insulating film, is used as a memory unit. In a data writing and erasing method for a semiconductor memory device, the absolute value of the drain potential applied to the drain region is
Data is written by setting the source potential to a value larger than the absolute value of the source potential applied to the source region, and the drain region is brought into a potential state that can prevent reverse current between the drain region and the substrate. At the same time, a predetermined potential that can prevent channel formation between the source region and the drain region is applied to the control gate, and the source potential having an absolute value larger than the absolute value of the drain potential is applied to the source potential. A data writing and erasing method for a semiconductor memory device, characterized in that data is erased by applying voltage to a region. 2) The data writing and erasing method for a semiconductor memory device according to claim 1, wherein the absolute value of the source potential during data erasing is set larger than the absolute value of the drain potential during data writing.