JPH03139934A - Clock generation circuit for demodulating cmi data - Google Patents

Abstract

PURPOSE:To automatically and optimumly set up phase relation between data and a clock by detecting a phase difference between a selected delay clock and an oscillation clock, and when the phase difference reaches a prescribed value, outputting the delay clock as the following data modulating timing clock. CONSTITUTION:A phase comparator 11 compares the phases between a selected delay clock 110 outputted from a multiplexer 9 and an oscillation clock 102, generates a phase difference signal 111 corresponding to the phase difference and a DC component comparator 12 compares the DC component of the signal 111 with the DC component of the clock 102, and when both the components coincide with each other, generates a coincidence detecting signal 112. A register 13 enters and holds the current value 108 of a counter 8 selected by the 2nd selector 7 in response to the signal 112. The stored contents 107 are inputted to the other input of the 2nd selector 7, and in a normal operation mode, the contents 107 stored in the register are outputted as the selection signal of the multiplexer 9. Consequently, the timing relation between data and clocks is made almost optimum in a CMI decoer 10.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a clock generation circuit for CMI data decoding;
In particular, the present invention relates to a clock generation circuit in a CMI data decoding circuit that decodes CMI data using a timing clock for data decoding extracted from CMI data.

A CMI decoder, which is a conventional CMI data decoding circuit, extracts a clock signal for data decoding from manually inputted CMI data, and decodes the CMI data using this extracted clock.

In this case, the optimum value of the phase difference between the timing clock for data decoding and the data to be decoded is π/2 radians, and therefore, the phase difference is adjusted to the optimum phase difference.
It is necessary to calm down. Conventionally, this adjustment has been done manually, and the method will be explained using the circuit shown in FIG.

CMI data at frequency fO is decoded by CMI decoder 1 ( ). In this case, the timing extraction circuit 4 generates a timing clock 110 for decoding from the frequency IF clock 104 extracted from the data.

For this purpose, a delay circuit 6 is provided, and this delay circuit 6 applies a delay of m (rn is an integer of 2 or more) to the extracted clock 104 to generate m delayed clocks 109. A multiplexer 9 and a switch 15 are provided to selectively derive the delayed clock 109 of this 01 tree, and this selected clock 110 is used as a decoding timing clock.

In this case, the relationship between data and timing clock is π/
It is optimal to set the phase difference to have a phase difference of 2 radians. Therefore, the adjuster monitors this phase relationship using an oscilloscope and sequentially switches the switches 15, and sets the delay clock timing when the optimum phase difference is reached. clock 1
It is set at 10.

As described above, in the conventional technology, the phase timing between the data and the tarokku is manually adjusted, which is time-consuming and labor-intensive, and has the disadvantage of lacking accuracy.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the prior art, and its 1-1 objective is to automatically set the order 1rl relationship between data and clock to an optimum level. The purpose is to share a clock generation circuit for CMI data decoding which is capable of CMI decoding.

Structure of the Invention According to the present invention, the CM! CM that decodes data! The clock generation circuit in the data decoding circuit includes oscillation means for oscillating a clock having the same frequency as the timing clock, and m types of delays (m is an integer of 2 or more) by adding λI to the oscillation clock. a delay means for generating m delay clocks by giving m delay clocks;
selection means for selectively deriving wooden delayed clocks sequentially at a predetermined period; and detecting that the phase difference between the selected delayed clock and the oscillation clock has reached a preset predetermined value. A clock generation circuit is characterized in that it includes a difference detection means and a means for outputting a delay clock selected at that time as a timing clock for data decoding in response to the detection timing of the detection means.
W is beaten.

Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, oscillator 1 has the same frequency fO as the CMI data.
The initializing pulse generator 2 is triggered by the clock phase and the initializing signal generated at the time of the decay instruction, and generates the initializing pulse 1 (11).

The RS flip-flop (FF) 14 is set by this initialization pulse 101, and enters the initialization mode (that is, the clock phase 1.1 adjustment mode).

Initialization mode by this FF14 responds to item 4, first and second selectors 3 and 7, register 1.
3 is controlled. The first selector 3 selects either the CMI data or the oscillation clock 102 of the oscillator 1, and selects the oscillation clock 102 in the initialization mode.

The second selector 7 selects either the output of the counter 8 or the output of the register 13, and selects the output of the counter 8 in the initialization mode.

The frequency dividing circuit 5 is the output clock 10 of the timing extraction circuit 4.
4 to 1/n, (1/fO)Xn>
τ (τ is the time constant of the integrator of the DC component comparison circuit 12), and the recounter 8 is counted up by this frequency-divided output [05.

In the initialization mode, the second selector 7 selects the value of the counter 8 and uses it as the selection signal for the multiplexer 9. Therefore, each time the content of the counter 8 is counted up from the initial value "0", the multiplexer 9 is The selection of the output clock IIO of the circuit 6 is sequentially switched.

Comparing circuit I11] 1 compares the phases of the selected delayed clock 110 of the multiplexer 9 and the oscillation clock 102, and generates a phase difference signal ill corresponding to the phase difference. The DC component comparison circuit 12 compares the DC component of the difference signal 111 with the DC component of the oscillation clock 102, and generates a match signal 112 when the two match.

In response to the occurrence of the coincidence signal 112, the register 13 takes in the current value 10B of the counter 8 selected by the second selector 7, and holds this value thereafter. The content [07 held in this register 8 becomes the input of the second selector 7, and in the normal operation mode, the content held in this register 107 becomes the selection signal of the multiplexer 9.

The carry output 113 of the counter 8 resets the FF 14, and the Q output 114 causes the first and second selectors 3 and 7 to switch to the normal mode and CM! When outputting data and output 107 of register 13 respectively)
1. Then, the counter 8 is reset, and the normal operation mode is entered from then on. In this normal operation mode, CMI data is manually input to the CMI decoder 1 ( ) and decoded by the timing clock IO from the multiplexer 9 .

FIG. 2 is a timing clock showing the waveforms of various signals indicating the operation of the blocks shown in FIG. When the initialization signal is input, the initialization pulse generation circuit 2 generates a one-shot initialization pulse 101. FF1
4 is set to the initialization mode by the initialization pulse 101 (high level output).

Since the first selector 3 selects and outputs the oscillation clock 102 that oscillates at the frequency fo in the initialization mode, the timing extraction circuit 4 outputs the extraction l cock [04 of this fO, which is processed by the delay circuit 6. r
q of na delays are obtained and output as an m-tree delay clock 109.

Counter 8 uses the divided clock l in the initialization mode.
The number of ports 5 is counted up to m, and count data 106 is output. In the initialization mode, the second selector 7 selects the count data 106 and outputs it as the second selector output signal 108.
The selection clock 110, which is the output of the multiplexer 9, is one period of the frequency divided clock [05 (n/f O[scc]
) can be switched every time. Thereby, the phase difference between the output signal 103 of the first selector 3 and the selection clock 110 can be changed stepwise as the counter 8 counts up.

The phase comparator circuit 11 receives the output 13 of the first selector 3.
A phase difference pulse tit with a pulse width corresponding to the phase difference between the CMI data break [1 and the rising (or falling) of the selected clock 110 and the selected clock 110 is output.

The DC component comparison circuit 12 is composed of an integrator (time constant τ) and a comparator.
DC level of the output signal 103 of the first selector 3
By comparing with 1/2 of the C level, the duty ratio of the phase strategy pulse IH reaches the boundary [1] where the duty ratio is 1/4.
The output DC component comparison signal 112 is changed. This point of change occurs when the desired order #lI difference is π/2, so at the timing of the change in the DC component comparison signal 112, the register 1
3 holds the count data toe.

When the counter 8 counts m pieces, the carry value is 113.
Exit, reset FF 14, and switch to normal operation mode. When switching to the normal operation mode, the second selector 7 selects the data held in the register 13, so the multiplexer 9 selects the output signal 1 of the first selector 3.
03 and the selected clock 110, the delay clock is output such that the difference in order tII is approximately π/2. Also 5
In the normal operation mode, the first selector 3 selects and outputs CMI data, so in the C to II decoder 1o,
The timing relationship between data and clock is almost optimal (
(The optimum difference between data and clock is -π/2.)

Effects of the Invention As explained in 2, according to the present invention, by automatically setting the delay 1ffi of the timing extracted clock to the optimum value, it is possible to manually calculate the 1 difference between the data and the tarok using an oscilloscope or the like. This eliminates the need to do the matching work, and has the advantage that it can be easily done by simply inputting the initialization signal manually.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the embodiment of the present invention, and FIG. 3 is a block diagram explaining a conventional technique. Explanation of symbols of main parts 1... Oscillator 6... Delay circuit 9... Multiplexer 10... CMI decoder 11... Phase comparison circuit 12...DC component comparison circuit 13...Register

Claims (1)

[Claims] (1) A C that decodes the CMI data using a timing clock for data decoding extracted from the CMI data.
A clock generation circuit in the MI data decoding circuit, comprising oscillation means for oscillating a clock having the same frequency as the timing clock, and m types of delays (m is an integer of 2 or more) for the oscillation clock. a delay means for generating m delayed clocks; a selection means for selectively deriving the m delayed clocks sequentially at a predetermined period; and a phase difference between the selected delayed clock and the oscillation clock is set in advance. phase difference detection means for detecting that a predetermined value has been reached; and means for outputting the currently selected delay clock as a timing clock for data decoding in response to the detection timing of the detection means. A clock generation circuit characterized by: