JPH03142385A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the test time and to reduce the circuit scale by providing a logic circuit, which supplies an input signal to an output buffer, with the normal operation logical processing function and the switching function and operating inside and outside areas by power sources independent of each other. CONSTITUTION:According as the level of a test signal TST is raised or reduced, the output level of an input buffer 1 rises or falls and transistors TRs T1 and T4 of plural logic circuits 3 (3A...) are turned off and on or turned on and off. In accordance with this operation, each circuit 3 is operated by an NOR circuit and performs the NOR processing of the output of an internal circuit 2 to execute the normal operation, or the test to set the output of an output buffer 4 (4A...) corresponding to the circuit 3 to the high level is performed. A supply voltage VDD2 of circuits 2 and 3 formed in the internal area is set to a value lower than the input threshold of the buffer 4 to perform the test to set the output of the buffer 4 to the low level. At this time, the output of the buffer 4 is set to the low level of the earth potential level independently of the logical value of the circuit 2 and the level of the signal TST.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a large number of output buffers.

[Conventional technology]

Conventionally, in this type of semiconductor integrated circuit, when performing characteristic tests such as the output voltage level and output current of each output buffer provided in the outer region, standard tests, etc., the first technique is as follows.
Continuous test signals (hereinafter referred to as test patterns) are sent from the test equipment to the input buffer provided in the outer area.
was input, and the output state was set to allow standard and characteristic tests of each output buffer to be performed using the outputs of internal circuits and logic circuits provided in the inner area. Therefore, it is necessary to create a test pattern for setting the output state, and it is also necessary to run the test pattern during the test, resulting in a long test time.

Therefore, a second technique was devised that allows the output states of all output buffers in the outer area to be set to the states necessary for testing, regardless of the test pattern.

FIGS. 3 and 4 are a block diagram and a transistor level circuit diagram of a semiconductor integrated circuit according to the second technique.

Input buffer I, IB and output buffer 4A are formed in the outer region, and internal circuit 2 and logic circuit 38. The switching circuit 5 is formed in the inner region.

The control signal CNT has a function of determining whether the operation mode of this semiconductor integrated circuit is a test mode or a normal operation mode.

When the normal operation mode is set by the control signal CNT, the result processed by the internal circuit 2 is input to the logic circuit 3x, and after predetermined logic processing (NOR processing) is performed in the logic circuit 3X, the switching circuit 5x and the output buffer The original processing of this semiconductor integrated circuit is to output (OUTI) to the outside via 4.

When the control signal CNT enters the test mode, the signals from the internal circuit 2 and the logic circuit 3x become invalid, and the test signal TSTx inputted via the input buffer lA becomes valid, and is sent to the output buffer 4 via the switching circuit 5x. Each test can be performed using the output 0UTI of the output buffer 4A.

This semiconductor integrated circuit has a large number of output buffers, but in FIGS. 3 and 4, one output buffer 4.
only is shown. Each of these output sofas is provided with a switching circuit (equivalent to 5X) and a logic circuit (equivalent to 3X).

[Problem to be solved by the invention]

In the first technique, the conventional semiconductor integrated circuit described above is configured to test the output buffer by operating internal circuits and logic circuits using a test pattern, so it is necessary to create a test pattern. There is a drawback that the test time depending on the test pattern becomes long, and the second
This technology requires the same number of switching circuits as output buffers, as well as two input buffers and input terminals for operating mode switching and test signal input, which has the disadvantage of increasing the circuit size. .

The purpose of the present invention is to eliminate the need for creating test patterns;
An object of the present invention is to provide a semiconductor integrated circuit capable of shortening test time and reducing circuit scale.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has an input buffer circuit that operates on a first power source and transmits a test signal, an internal circuit that operates on a second power source and performs a predetermined function, and an internal circuit that operates on the second power source. , when the test signal input through the input buffer circuit is at a first level, it becomes a predetermined level, and when it is at a second level, a predetermined logical processing is performed on the output signal of the internal circuit. It has a plurality of logic circuits that output signals having the resulting level, and a plurality of output buffer circuits that each operate on the first power supply and transmit the output signal of the corresponding logic circuit to the output end. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 and 2 are a block diagram and a transistor level circuit diagram, respectively, showing one embodiment of the present invention.

In this embodiment, the power supply voltage VDD1 is formed in the outer region.
an input buffer l that operates on a first power supply of and transmits a test signal TST;
An internal circuit 2 that operates on the second power supply of D2 and performs a predetermined function, and an internal circuit 2 that is formed in the inner region and operates on the second power supply, serves as an input buffer bell, and when the power supply voltage VDDI is at a high level. A plurality of logic circuits 3 that output a signal having a level resulting from performing predetermined logic processing on the output signal of the internal circuit 2. A, 3B, and the corresponding logic circuits (3A
, 3B) to the output end.

Next, the operation of this embodiment will be explained.

Now, when the test signal TST is set to a low level, the output of the input buffer l becomes a low level, so the transistor Tl of the logic circuit 3.4 turns on, the transistor T4 turns off, and the output of the logic circuit 3A becomes the internal circuit 2. The level is high regardless of the output. Therefore, a test can be performed in which the outputs of the output buffers 4A and 4B are set to high level.

Next, when the test signal TST is set to a high level, the output of the input buffer l becomes a high level, so the transistor TI of the logic circuit 3A is turned off and the transistor T4 is turned on, so that the logic circuit 3 operates as a NOR circuit. ', is the result of performing NOR processing on the output of the internal circuit 2.

In other words, it is in a normal operating state.

In the above operation, the power supply voltage VflDI r ”D
D2 may have the same voltage.

Next, output buffers 4A, 4. A test in which the output of
Regardless of the level of ST, it is at a low level of the ground potential level.

〔Effect of the invention〕

As explained above, the present invention provides a logic circuit that supplies an input signal to an output buffer formed in an outer region, so that when the test signal is at the first level, the test signal is at a preset fixed level, and when the test signal is at the first level, the test signal is at a preset fixed level; When the logic circuit is at the level, the logic processing function and switching function in normal operation output a signal that has the level as a result of performing predetermined logic processing on the output of the internal circuit formed in the inner area together with this logic circuit. By using a configuration in which the outer area and inner area operate with separate power supplies, there is no need to perform tests using test patterns as in the past, eliminating the need to create test patterns and shortening test time. Moreover, the number of independent switching circuits equal to the number of output buffers is not required, and the number of input buffers and input terminals is reduced from two to one, which has the effect of reducing the circuit scale.

[Brief explanation of the drawing]

1 and 2 are a block diagram and a transistor level circuit diagram showing an embodiment of the present invention, respectively, and FIGS. 3 and 4 are a block diagram and a transistor level circuit diagram showing an example of a conventional semiconductor integrated circuit, respectively. It is a circuit diagram. 1, l, , 11...input buffer, 2
...Internal circuit, 3. ,,3B, 3,...
...Logic circuit, 4A, 41...Output buffer, 5
x...Switching circuit, TI-T6...Transistor.

Claims (1)

[Claims] An input buffer circuit that operates on a first power source and transmits a test signal, an internal circuit that operates on a second power source and performs a predetermined function, and an internal circuit that operates on the second power source and transmits the test signal through the input buffer circuit. When the input test signal is at the first level, it becomes a predetermined level, and when it is at the second level, it outputs a signal that becomes the level that is the result of performing predetermined logic processing on the output signal of the internal circuit. A semiconductor integrated circuit comprising: a plurality of logic circuits; and a plurality of output buffer circuits each operating on the first power supply and transmitting an output signal of the corresponding logic circuit to an output terminal.