JPH03132111A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a delay time from increasing even when a test circuit is incorporated by providing plural output circuits receiving a test result signal or a function logic signal, supplying a relevant output signal to a common output terminal and having a midpoint of CMOS transistors(TRs) reaching a high impedance state with a control signal. CONSTITUTION:Midpoints Md, Mt of CMOS TRs of an output circuit 1 outputting an output signal Sd corresponding to a function logic signal SD and an output circuit 2 outputting an output signal St corresponding to a test result signal ST are connected to an output terminal Do. One circuit is neglected by fixing an inverse of OET input or an inverse of OE input to a high level. That is, the output circuit 1 is similar to a circuit in the absence of the test circuit 4 substantially and no excess selection circuit is provided, then the delay time is saved. Thus, the state of the test circuit 4 is outputted without increasing the delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device incorporating a test circuit.

[Conventional technology]

As shown in FIG. 3, conventionally, a semiconductor device incorporating a test circuit 4 has an input terminal that receives a functional logic signal SI) of a functional circuit 3 that operates the original function of the semiconductor device, and a test result of the test circuit 4. It has an input terminal T that receives a signal ST, and either one of the two signals SD or ST is connected to a control signal CIl.
Selection circuit 1 selected by C2. It had a selection output circuit 21 in which the output circuit 1 and the output circuit 1 were connected in series.

The middle point M of 0MO8 of the output circuit 1 is one of the king states of the control signal pedance.

[Problem to be solved by the invention]

Since the conventional semiconductor device described above has a logic circuit that selects and combines the original operating state and the test state, the number of logic stages for the selection circuit increases compared to a case where the test circuit is not built-in.

Therefore, the functional logic signal has the disadvantage that the delay time is increased by the amount of time it passes through the logic circuit before being output, and this has been a particular obstacle to the recent demands for high-speed operation.

[Means to solve the problem]

The semiconductor device of the present invention inputs an internal functional logic signal or a test result signal, supplies the corresponding output signal to a common external output terminal, and enters a 0MO3) transistor that is brought into a high impedance state by a control signal. It is configured to include a plurality of output circuits having a plurality of points.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

Inputting the original functional logic signal SD, the corresponding output signal S,
CM of each of the output circuit 1 that outputs the test result signal S, and the output circuit 2 that outputs the output signal S corresponding to the test result signal S.
The middle point Md1M of the OS transistor is both the output terminal D0
is connected to.

When outputting the original logical operation, the OET input is fixed at a high level and the output state of the output circuit 2 is set to a high impedance state.

By doing this, D
Depending on the input and OE large input combination state, the output terminal D0 can output a high level, a low level, or a high impedance state.

On the other hand, by fixing the σ blindness to a high level, the output of the output circuit 1 becomes a high impedance state, and the test result signal S
T is output to Do when OET is at a low level.

When OET is at a high level, Do is in a high impedance state.

Since the output circuit 2 is used exclusively for outputting the test result signal S, high-speed operation is not required. Therefore, the transistor size of the output circuit 2 may be small, and the load stray capacitance of the output circuit 2 when viewed from the output circuit 1 is small. can be ignored.

Further, the output circuit 1 is substantially the same as the circuit without the test circuit 4, and the unnecessary selection circuit 1 in FIG. The output circuit 11 is an output circuit for outputting the original functional logic signal SD, and the output circuits 12 and 13 for outputting the test result signal S T l 1ST2 are The middle point M of the transistor 0MO3) is connected to the output terminal D0.

When performing the original operation, the lower T is fixed at a high level, T2 is fixed at a low level, and the outputs of the output circuits 12 and 13 are kept in a high impedance state.

In this case, the input signal is 100. Depending on the combination of the OE and OE input signals, the output terminal D0 can output a high level, a low level, or a high impedance state.

On the other hand, by fixing OE to a low level, the output of the output circuit 11 is placed in a high impedance state.

When the test result signal St+ of T2 is at a low level, the output circuit 12 outputs a high level, and the test result signal S of T2 is
When t□ is at a high level, the output circuit 13 outputs a low level, which is output to Do.

However, the low level of S,1 and the high level of ST2 are controlled so as not to occur simultaneously.

Since the output circuit 11 is connected in parallel with the output circuits 12 and 13 of the test circuit 4 in the same way as the output circuit 1 of FIG. 1 described above, there is no increase in the delay time of functional data.

Moreover, since each of the output circuits 12 and 13 is composed of one transistor, no special consideration is required for the arrangement on the chip of the semiconductor device.

〔Effect of the invention〕

As explained above, the present invention has the effect of outputting the state of a test circuit without increasing the delay time by commonly connecting the output terminals of a plurality of output circuits capable of outputting a high impedance state to an external terminal. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the invention, FIG. 2 is a circuit diagram of a second embodiment of the invention, and FIG. 3 is a circuit diagram of an example of a conventional semiconductor device. 1.2.11-13... Output circuit, 3...
...Functional circuit, 4...Test circuit, 5-7...
...NAND gate, Do...external output terminal, M...middle point of CMOS transistor, SD
...Functional logic signal, S, ...Test result signal.

Claims (1)

[Claims] A plurality of output circuits each having a midpoint of a CMOS transistor that inputs an internal function logic signal or a test result signal and supplies a corresponding output signal to a common external output terminal, and that is brought into a high impedance state by a control signal. A semiconductor device comprising: