JPH0314256B2 - - Google Patents

Info

Publication number
JPH0314256B2
JPH0314256B2 JP3292284A JP3292284A JPH0314256B2 JP H0314256 B2 JPH0314256 B2 JP H0314256B2 JP 3292284 A JP3292284 A JP 3292284A JP 3292284 A JP3292284 A JP 3292284A JP H0314256 B2 JPH0314256 B2 JP H0314256B2
Authority
JP
Japan
Prior art keywords
packet
input data
change
period
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3292284A
Other languages
Japanese (ja)
Other versions
JPS60177758A (en
Inventor
Masato Hayakawa
Shogo Maruyama
Shunichi Terai
Tadashi Kishida
Koji Itoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Chubu Electric Power Co Inc
Mitsubishi Electric Corp
NEC Corp
Original Assignee
Fujitsu Ltd
Chubu Electric Power Co Inc
Mitsubishi Electric Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Chubu Electric Power Co Inc, Mitsubishi Electric Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP59032922A priority Critical patent/JPS60177758A/en
Publication of JPS60177758A publication Critical patent/JPS60177758A/en
Publication of JPH0314256B2 publication Critical patent/JPH0314256B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Selective Calling Equipment (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はパケツト交換ネツトワークのパケツ
ト送信装置におけるパケツト組立タイミングの制
御方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for controlling packet assembly timing in a packet transmitter of a packet switching network.

〔従来技術〕[Prior art]

従来、この種の制御方式は、例えば、電力系統
状態監視用の入力データの場合では、ネツトワー
ク内の負荷を考慮し、入力データに表わされる情
報の意味を失わない程度の適当な時間間隔で予め
指定された情報源単位に入力データを標本化し、
パケツトに組立て伝送する定周期組立（このよう
に組立てるパケツトを以降定周期パケツトと称
す）を基本に伝送し、上記電力系統の状態変化に
よる入力データの変化を検知したときには直ちに
予め指定された情報源単位にその変化データを含
む入力データをパケツトに組立て伝送する即時組
立（このように組立てるパケツトを以降状変パケ
ツトと称す）を組合せた方式がとられている。と
ころでこのような制御方式でデータを扱うパケツ
ト交換ネツトワークでは、通例時々刻々と変化す
る電力系統状態の特性から、一旦送信したパケツ
トの誤り再送は行つていない。 Conventionally, this type of control method, for example, in the case of input data for power system status monitoring, takes into account the load within the network and analyzes the input data at appropriate time intervals to the extent that the meaning of the information represented in the input data is not lost. Sample the input data in units of pre-specified information sources,
Transmission is based on periodic assembly (packets assembled in this way are hereinafter referred to as fixed periodic packets) in which data is assembled into packets and transmitted, and when a change in input data due to a change in the state of the power system is detected, it is immediately transmitted to a pre-specified information source. A method is used that combines instant assembly in which input data including the changed data is assembled into packets and transmitted (packets assembled in this way are hereinafter referred to as changed packets). By the way, in a packet switching network that handles data using such a control method, packets that have been once transmitted are not retransmitted in error due to the characteristics of the power system state, which usually changes from moment to moment.

従つて、状変パケツトのネツトワーク内での消
失があつた場合、受信側でのデータの回復は、次
の定周期パケツトの受信まで待たねばならず、こ
のため、電力系統の状態変化時のきめの細かいデ
ータが得られず、電力系統状態の監視、制御を精
度よくできなかつた。 Therefore, when a status change packet is lost in the network, data recovery on the receiving side must wait until the next periodic packet is received. Detailed data could not be obtained, making it impossible to accurately monitor and control the power system status.

さらにまた、従来の電力系統状態変化時の処理
は、電力系統状態を監視、制御するパケツト受信
装置側が、ネツトワークを介して受信される状変
パケツトまたはその後の定周期パケツトに含まれ
る変化データと入力データ変化発生時点の周辺デ
ータを組合せて行つており、電力系統変化時の処
理に必要な付帯情報である関連する周辺データが
多い場合には、パケツト送信装置側で、予め複数
の論理チヤネルを割当ておき、入力データ変化の
検知時に、一方の論理チヤネル上での変化データ
と一部の周辺データから成る状変パケツトの即時
組立および送信と、他方の論理チヤネル上での該
変化データに関連するその他の周辺データから成
る定周期パケツトの定周期組立ておよび送信を行
つている。 Furthermore, in the conventional processing when power system status changes, the packet receiving device that monitors and controls the power system status receives change data from status change packets received via the network or subsequent periodic packets. This is done by combining the peripheral data at the time of the input data change, and if there is a lot of related peripheral data that is supplementary information necessary for processing when the power system changes, the packet transmitter side can create multiple logical channels in advance. When a change in input data is detected, immediate assembly and transmission of a change packet consisting of the change data and some surrounding data on one logical channel and associated change data on the other logical channel are performed. It performs periodic assembly and transmission of periodic packets consisting of other peripheral data.

従つて電力系統状態変化に係わる周辺データが
多い場合、電力系統状態監視を制御するパケツト
受信装置側が電力系統状態変化に関する全情報を
受信するためには、一方の論理チヤネルから受信
される状変パケツトと、状変パケツト送信後の定
周期時間経過後に他方の論理チヤネルから受信さ
れ関連するデータの定周期パケツトが必要とな
り、電力系統状態変化に対する監視制御が遅れる
ため精度のよい監視・制御ができないという欠点
があつた。 Therefore, when there is a large amount of peripheral data related to power system status changes, in order for the packet receiving device that controls power system status monitoring to receive all information regarding the power system status changes, it is necessary to use status change packets received from one logical channel. Then, a fixed periodic packet of related data received from the other logical channel is required after a fixed period of time has elapsed after the status change packet is sent, which delays monitoring and control of power system state changes, making it impossible to perform accurate monitoring and control. There were flaws.

〔発明の概要〕[Summary of the invention]

この発明の目的は、上記の欠点の改善のために
入力データの変化を検知後、入力データのパケツ
ト組立周期を短かくして、複数回伝送しかつこの
入力データ変化を検知後、予め自局のテーブルに
関連付けられた他の情報源の入力データのパケツ
ト組立周期をも短かくして、複数回伝送すること
によりより高速で確実な状態監視が行なえる制御
方式を提供する所にある。 An object of the present invention is to shorten the cycle of assembling input data packets after detecting a change in input data to improve the above-mentioned drawbacks, and to transmit the input data multiple times. The purpose of the present invention is to provide a control method that can perform faster and more reliable status monitoring by shortening the packet assembly cycle of input data from other information sources associated with the information source and transmitting it multiple times.

〔発明の実施例〕[Embodiments of the invention]

以下、第１図乃至第３図にもとづきこの発明の
一実施例を説明する。 An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

第１図は、この発明に関連するパケツト送信装
置とパケツト交換ネツトワークの関係を示すもの
で、パケツト送信装置１は複数個のデータ送信端
末２ａ〜２ｎの夫々の入力データ３ａ〜３ｎをパ
ケツト４ａ〜４ｍに組立て、特定の論理チヤネル
５ａ〜５ｍを使用して伝送する。パケツト受信装
置６はこれらの論理チヤネル５ａ〜５ｍを介して
受信したパケツト４ａ〜４ｍを分解して出力デー
タ７ａ〜７ｌをデータ受信端末８ａ〜８ｌへ配信
する。 FIG. 1 shows the relationship between a packet transmitting device and a packet switching network related to the present invention. A packet transmitting device 1 transfers input data 3a to 3n from a plurality of data transmitting terminals 2a to 2n to a packet 4a. ~4m and transmit using specific logical channels 5a~5m. Packet receiving device 6 disassembles packets 4a-4m received via these logical channels 5a-5m and delivers output data 7a-7l to data receiving terminals 8a-8l.

第２図は、第１図のパケツト送信装置の動作を
説明するためのブロツク図で、この発明の該当部
位であるパケツト組立契機監視部９、パケツト組
立部１０、パケツト組立契機管理部１１とその他
部位との関係を示す。パケツト組立契機監視部９
は、データ送信端末２ａ〜２ｎから受信される入
力データ３ａ〜３ｎを格納する端末情報入力エリ
ア１２の入力データ３ａ〜３ｎの変化を監視し、
変化がない場合は予め指定された周期でパケツト
組立部１０を起動する。入力データ３ａ〜３ｎに
変化が検知された場合は上記周期と関係なく直ち
にパケツト組立部１０を起動する。この際、起動
すべき（パケツト組立てを行う）論理チヤネルを
指定し、即時起動であることを明示する。パケツ
ト組立部１０は即時起動された場合、個々の論理
チヤネルのパケツト組立タイミングを記述したパ
ケツト組立契機管理部１１の中から、予め指定さ
れた論理チヤネル箇所の周期変更指示フラグ１３
を参照し、周期変更指示が有りの場合には同パケ
ツト組立契機管理部１１の中の周期変更回数指定
フイールド１４に第２の定周期T2パケツト組立
てをＮ回（例えばＮ＝４）継続する情報を設定し
た後、指定された論理チヤネルの状変パケツト組
立てを行う。周期変更指示がない場合には、単に
指定された論理チヤネルのみの状変パケツト組立
てを行う。パケツト組立部１０は起動された場
合、まずパケツト組立契機管理部１１の中の周期
変更回数指定フイールド１４のＮの内容を調べ、
Ｎ＝０（状変パケツトの組立てに継続して、周期
を短かくしたパケツトを組立てる必要がない。）
の場合、次に該周期が第１の定周期パケツトの組
立周期T1に一致するか否かを調べ、一致すれば
パケツト組立契機管理部１１の中から第１の定周
期パケツト組立周期T1の論理チヤネル群を選択
し、それらの論理チヤネルの定周期パケツトを組
立てる。一致しなければ定周期パケツトの組立て
は行わない。Ｎ＝１以上（状変パケツトの組立て
に継続して、周期を短かくしたパケツトを組立て
る必要がある。）の場合、次に該周期が第２の定
周期パケツトの組立周期T2に一致するか否かを
調べ、一致すればパケツト組立契機管理部１１の
中から周期変更指示フラグ１３により予め、入力
データ変化による周期変更が指定されている論理
チヤネル群を選択し、それらの論理チヤネルの第
２の周期の定周期T2パケツトを組立て、この後
周期変更回数指定フイールド１４の値を１減算す
る。一致しなければ、定周期パケツトの組立は行
なわない。 FIG. 2 is a block diagram for explaining the operation of the packet transmitting device shown in FIG. Indicates the relationship with the parts. Packet assembly trigger monitoring department 9
monitors changes in the input data 3a to 3n in the terminal information input area 12 that stores the input data 3a to 3n received from the data transmission terminals 2a to 2n,
If there is no change, the packet assembling unit 10 is activated at a pre-specified period. When a change is detected in the input data 3a to 3n, the packet assembling section 10 is immediately activated regardless of the above-mentioned cycle. At this time, the logical channel to be activated (packet assembly is performed) is specified, and the immediate activation is specified. When the packet assembling unit 10 is activated immediately, it selects the cycle change instruction flag 13 of a pre-specified logical channel location from the packet assembly trigger management unit 11 that describes the packet assembling timing of each logical channel.
If there is a cycle change instruction, the second fixed cycle T2 packet assembly is continued N times (for example, N = 4) in the cycle change number designation field 14 in the packet assembly trigger management unit 11. After setting the information, the status change packet of the specified logical channel is assembled. If there is no cycle change instruction, state change packets are simply assembled for only the designated logical channel. When the packet assembling unit 10 is started, it first checks the contents of N in the cycle change number designation field 14 in the packet assembly trigger management unit 11, and
N=0 (There is no need to assemble a packet with a shorter cycle following the assembly of a changed packet.)
In this case, it is next checked whether the period matches the first periodic packet assembly period T 1 , and if they match, the first periodic packet assembly period T 1 is selected from the packet assembly trigger management unit 11 . selects a group of logical channels and assembles periodic packets of those logical channels. If they do not match, the periodic packet is not assembled. If N = 1 or more (it is necessary to assemble a packet with a shortened period following the assembly of a state-changed packet), then the period matches the assembly period T 2 of the second fixed-period packet. If they match, a logical channel group for which period change due to input data change is specified in advance by the period change instruction flag 13 is selected from the packet assembly trigger management unit 11, and the A fixed period T2 packet with a period of 2 is assembled, and then the value of the period change number specification field 14 is subtracted by 1. If they do not match, the periodic packet is not assembled.

上記パケツト組立部１０におけるパケツト組立
ては、予め確保するパケツトバツフア１５のパケ
ツト情報部１６に格納するデータの、端末情報入
力エリア１２内でのアドレス情報や、パケツトヘ
ツダ部１７の元情報などが予め設定されている論
理チヤネル毎のパケツト組立手順テーブル１８を
参照して行う。 Packet assembly in the packet assembling section 10 is performed by setting the address information in the terminal information input area 12 and the original information in the packet header section 17 of the data to be stored in the packet information section 16 of the packet buffer 15 secured in advance. This is done by referring to the packet assembly procedure table 18 for each logical channel.

第３図は、第２図で述べた動作をタイミングチ
ヤートで表わしており、入力データ変化に伴う、
パケツト組立周期変更を指定された論理チヤネル
５ａにおける入力データ変化以前と入力データ変
化時および入力データ変化後のパケツト組立状況
を示す。論理チヤネル５ａは、入力データ変化が
発生する以前は、第１の定周期T1で定周期パケ
ツト１９を組立てており、入力データ変化発生時
点では状変パケツト２０を組立てる。状変パケツ
ト組立後では、パケツト組立周期を第２の周期
T2に早めた定周期パケツト２１の組立てを４回
行い、再びパケツト組立周期を第１の周期T1に
復帰した定周期パケツト２２の組立てを行う。 FIG. 3 shows the operation described in FIG. 2 as a timing chart.
The packet assembly status before, at the time of, and after the input data change in the logical channel 5a designated to change the packet assembly cycle is shown. The logical channel 5a assembles a fixed period packet 19 at the first fixed period T1 before a change in input data occurs, and assembles a state change packet 20 at the time when a change in input data occurs. After assembling the state-changed packet, the packet assembly cycle is changed to the second cycle.
The fixed-cycle packet 21 is assembled four times with the packet assembly cycle accelerated to T2 , and the fixed-cycle packet 22 is assembled again with the packet assembly cycle returned to the first cycle T1 .

第４図は、第２図で述べた動作をタイミングチ
ヤートで表わしており、入力データ変化に伴うパ
ケツト組立周期変更を指定された論理チヤネル群
５ｂ，５ｃにおける入力データ変化以前と入力デ
ータ変化時（第４図では論理チヤネル５ｂに関連
する入力データに変化が生じた場合を例示する）
および入力データ変化後のパケツト組立状況を示
す。論理チヤネル５ｂおよび５ｃは、入力データ
変化が発生する以前は、第１の定周期T1で定周
期パケツト２３を組立てており、論理チヤネル５
ｂに関連する入力データに変化が発生した時点で
は論理チヤネル５ｂに関する状変パケツト２４を
組立てる。論理チヤネル５ｂに関する状変パケツ
ト組立後では、パケツト組立周期を第２の周期
T2に早めた論理チヤネル５ｂおよび５ｃの定周
期パケツト２５の組立てを４回行い、再びパケツ
ト組立を第１の組立周期T1に復帰した論理チヤ
ネル５ｂおよび５ｃの第１の周期パケツト２６の
組立てを行う。 FIG. 4 shows the operation described in FIG. 2 as a timing chart, and shows the timing before and after the input data change in the logical channel groups 5b and 5c, which are designated to change the packet assembly cycle due to the input data change. (Figure 4 illustrates a case where a change occurs in the input data related to the logical channel 5b)
and shows the packet assembly status after input data changes. Before the input data change occurs, the logical channels 5b and 5c assemble the fixed period packets 23 at the first fixed period T1 , and the logical channels 5b and 5c
When a change occurs in the input data related to the logical channel 5b, a status change packet 24 related to the logical channel 5b is assembled. After assembling state-changed packets regarding logical channel 5b, the packet assembling period is changed to the second period.
The assembling of the fixed period packets 25 of the logical channels 5b and 5c accelerated to T2 is performed four times, and the assembly of the first periodic packets 26 of the logical channels 5b and 5c is performed again with the packet assembly returned to the first assembling period T1 . I do.

なお、上記実施例では、第２の周期で４回（Ｎ
＝４）伝送する場合について説明したが、Ｎの回
数は、Ｎ≧１であれば同様の効果を奏す。 Note that in the above embodiment, the number of times (N
=4) Although the case of transmission has been described, the same effect can be achieved as long as the number of times N is N≧1.

また、第１の周期T1と第２の周期T2との関係
は、T1＞T2の関係を満していれば、同様の効果
を奏す。 Furthermore, if the relationship between the first period T 1 and the second period T 2 satisfies the relationship T 1 >T 2 , the same effect will be achieved.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明の制御方式によれば入
力データの変化を検知したことにより送信するパ
ケツト組立周期を短かくしたので確実かつ高速に
伝送でき、またこの検知により予め関連づけした
他の情報源の入力データのパケツト組立周期をも
短かくするようにしたので確実かつ高速に伝送で
きる利点があり、状態監視制御の精度向上を図る
ことができる。 As described above, according to the control method of the present invention, the cycle of assembling packets to be transmitted is shortened by detecting a change in input data, which enables reliable and high-speed transmission. Since the packet assembly period for input data is also shortened, there is an advantage that reliable and high-speed transmission is possible, and the accuracy of condition monitoring control can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明に関連するパケツト送信装置
とパケツト交換ネツトワークの関係を示す図、第
２図はこの発明によるパケツト送信装置の一実施
例を示すブロツク図、第３図及び第４図は第２図
の動作を説明するためのパケツト組立タイミン
グ・チヤートである。 第２図乃至第４図において１はパケツト送信装
置、２はデータ送信端末、３は入力データ、５
ａ，５ｂ，５ｃは論理チヤンネル、９はパケツト
組立契機監視部、１０はパケツト組立部、１１は
パケツト組立契機管理部、１２は端末情報入力エ
リア、１３は周期変更指示フラグ、１４は周期変
更回数指定フイールド、１５はパケツトバツフ
ア、１６はパケツト情報部、１７はパケツトヘツ
ダ部、１８はパケツト組立手順テーブル、１９，
２３は定周期パケツト、２０，２４は状変パケツ
ト、２１，２５は第２の周期の定周期パケツト、
２２，２６は第１の周期の定周期パケツトであ
る。なお、上記各図中同一符号は同一または相当
部分である。 FIG. 1 is a diagram showing the relationship between a packet transmitting device and a packet switching network related to the present invention, FIG. 2 is a block diagram showing an embodiment of the packet transmitting device according to the present invention, and FIGS. 3 and 4 are This is a packet assembly timing chart for explaining the operation of FIG. 2. In FIGS. 2 to 4, 1 is a packet transmitting device, 2 is a data transmitting terminal, 3 is input data, and 5 is a packet transmitting device.
a, 5b, 5c are logical channels, 9 is a packet assembly trigger monitoring unit, 10 is a packet assembly unit, 11 is a packet assembly trigger management unit, 12 is a terminal information input area, 13 is a cycle change instruction flag, and 14 is the number of cycle changes. Designation field, 15 is a packet buffer, 16 is a packet information section, 17 is a packet header section, 18 is a packet assembly procedure table, 19,
23 is a fixed periodic packet, 20 and 24 are status change packets, 21 and 25 are fixed periodic packets of the second period,
22 and 26 are fixed periodic packets of the first period. Note that the same reference numerals in each of the above figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 １ 同一情報源の入力データを周期的にパケツト
化し、伝送するパケツト交換ネツトワークにおい
て、パケツト発信局において入力データを監視
し、入力データ変化がない期間は、第１の定周期
時間T1毎にパケツト組立てを行い、予め指定さ
れた情報源の入力データ変化が検知された場合、
パケツト組立周期を第１の定周期時間T1より短
かい第２の定周期時間T2で複数回（Ｎ回）伝送
することを特徴とするパケツト組立タイミング制
御方式。 ２ 同一情報源の入力データを周期的にパケツト
化し、伝送するパケツト交換ネツトワークにおい
て、パケツト発信局において入力データを監視
し、入力データ変化がない期間は、第１の定周期
時間T1毎にパケツト組立てを行い、予め指定さ
れた情報源の入力データ変化が検知された場合、
予め自局テーブルで関連付けられた他情報源の入
力データのパケツト組立周期をも、第１の定周期
時間T1より短かい第２の定周期時間T2で複数回
（Ｎ回）伝送することを特徴とするパケツト組立
タイミング制御方式。[Scope of Claims] 1. In a packet switching network in which input data from the same information source is periodically packetized and transmitted, input data is monitored at a packet originating station, and during a period in which there is no change in input data, a first constant is set. Packets are assembled every cycle time T1 , and when a change in input data from a pre-specified information source is detected,
A packet assembly timing control method characterized in that the packet assembly cycle is transmitted a plurality of times (N times ) at a second fixed cycle time T2 shorter than the first fixed cycle time T1. 2. In a packet-switched network that periodically packetizes and transmits input data from the same information source, the input data is monitored at the packet source station, and during a period when there is no change in the input data, the packet is transmitted every first periodic period T1 . When the packet is assembled and a change in input data from a pre-specified information source is detected,
The packet assembly cycle of input data from other information sources associated in advance in the own station table is also transmitted multiple times (N times) at a second fixed cycle time T2 that is shorter than the first fixed cycle time T1 . A packet assembly timing control method characterized by:
JP59032922A 1984-02-23 1984-02-23 Packet assembly timing control system Granted JPS60177758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59032922A JPS60177758A (en) 1984-02-23 1984-02-23 Packet assembly timing control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59032922A JPS60177758A (en) 1984-02-23 1984-02-23 Packet assembly timing control system

Publications (2)

Publication Number Publication Date
JPS60177758A JPS60177758A (en) 1985-09-11
JPH0314256B2 true JPH0314256B2 (en) 1991-02-26

Family

ID=12372393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59032922A Granted JPS60177758A (en) 1984-02-23 1984-02-23 Packet assembly timing control system

Country Status (1)

Country Link
JP (1) JPS60177758A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0376343A (en) * 1989-08-18 1991-04-02 Oki Electric Ind Co Ltd Packet processing equipment
JP4890513B2 (en) * 2008-08-01 2012-03-07 富士通テレコムネットワークス株式会社 Packet collection and delivery system

Also Published As

Publication number Publication date
JPS60177758A (en) 1985-09-11

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