JPH05110603A - Packet transmitter - Google Patents

Abstract

PURPOSE:To prevent the increase in a load of a CPU and a packet exchange by managing a timing when a composition request of plural packets takes place simultaneously. CONSTITUTION:A packet start signal received by packet start processing sections 4(1)-4(n) is stored in packet composition request storage sections. When a packet composition timing takes place in a reference timing management section 6, a packet start timing correction section 3 reads a packet composition counter to set the count to a variable (i). A packet composition request stored in the packet composition request storage sections is extracted one by one in the timing and sent to a packet composition processing section 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet transmission device for transmitting assembled packets using a packet switching network.

[0002]

2. Description of the Related Art In a conventional example, when assembling a plurality of packets to be transmitted to different destinations, each packet is assembled and transmitted at an independent timing.

FIG. 3 is a block diagram of a conventional transmission device. The data is input to the packet assembly processing unit 2 through the input processing unit 1. On the other hand, the packet activation processing unit 4 (1)-
At 4 (n), a packet activation signal is received for each packet, and a packet assembly request is issued to the packet assembly processing unit 2 at the reception timing. Upon receiving the assembly request from the packet activation processing units 4 (1) to 4 (n), the packet assembly processing unit 2 assembles the packet based on the input data and sends the packet through the output processing unit 5.

[0004]

As described above, in the conventional example, since the assembly of a plurality of packets is managed at independent timings, when the assembly requests of a plurality of packets are simultaneously generated, the packets are instantaneously transmitted. The load on the assembly process increases. Further, since a plurality of packets are transmitted at the same time, there is a drawback that the load on the packet switch is momentarily increased.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a packet transmission device which suppresses an instantaneous increase in load on a CPU and a packet switch.

[0006]

The present invention receives, for each packet, a packet activation signal corresponding to the packet,
In a packet transmission device provided with a packet start processing unit for generating a packet assembly request signal in response to the packet start signal and a packet assembly processing unit for assembling the packet at a timing when the packet assembly request signal is given, A reference timing management unit that independently generates a reference timing at fixed intervals and a packet assembly request signal, and a packet assembly request signal corresponding to the packet when the reference timing occurs. It is characterized by including a packet activation timing correction unit for extracting each packet from the packet assembly processing unit 2 and providing it to the packet assembly processing unit 2.

Here, the packet activation timing correction unit stores a packet assembly request storage unit for each packet in the order in which the packet assembly request signal is received, a packet assembly counter for designating a packet to be assembled at the time of receiving the reference timing, and A packet assembling transmission unit, which extracts packet assembly requests designated by the packet assembling counter one by one from the packet assembling storage unit and gives the packet assembling processing unit 2 to the packet assembling processing unit 2, may be provided.

[0008]

The n packet activation signals received by the packet activation processing unit are stored in each of the n packet assembly request storage units, and the packet activation timing correction unit 3 operates according to the packet assembly timing from the reference timing management unit. The packet assembly counter is read out and set to the variable i, and at that timing, the packet assembly requests stored in the i-th packet assembly request storage unit are taken out one by one and transmitted to the packet assembly processing unit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a functional block diagram of the transmission device of this embodiment.

In this embodiment, as shown in FIG.
A packet activation processing unit 4 that receives a packet activation signal corresponding to each packet for each packet and generates a packet assembly request signal according to the packet activation signal, and assembles the packet at the timing when the packet assembly request signal is given. A packet assembly processing unit 2 for performing the above, and as a feature of the present invention, further stores a reference timing management unit 6 that independently generates a reference timing at a constant interval for each packet, and a packet assembly request signal. The packet start timing correction unit 3 extracts the packet assembly request signal corresponding to the packet when the reference timing is generated from the stored packet assembly request signal and gives the packet assembly processing unit 2 with the packet start timing correction unit 3.

Next, the operation of each part of this embodiment will be described with reference to FIG.
This will be described with reference to (A). The data is input to the packet assembly processing unit 2 through the input processing unit 1. The packet activation processing units 4 (1) to 4 (n) receive the packet activation signal for each packet, and make a packet assembly request to the packet assembly processing unit 2 through the packet activation timing correction unit 3. The packet activation timing correction unit 3 corrects the timing of the packet assembly request received from the packet activation processing units 4 (1) to 4 (n) to the timing managed by the reference timing management unit 6, and sends it to the packet assembly processing unit 2. Request packet assembly.

Next, the packet start timing correction unit 3 will be described in detail. FIG. 1B and FIG. 2 are diagrams showing the configuration and operation of the packet activation timing correction unit 3.

The packet start timing correction unit 3 is shown in FIG.
As shown in (B), the packet assembly request storage unit 7 that stores the packet assembly request signal for each packet in the order of reception.
, A packet assembly counter 9 for designating a packet to be assembled at the time of receiving the reference timing, and packet assembly requests designated by the packet assembly counter from the packet assembly storage unit 7 one by one in order and given to the packet assembly processing unit 2. The packet assembling / transmitting unit 8 is provided.

Next, the operation of this embodiment will be described with reference to FIGS. 1 (B) and 2. Packet activation processing unit 4
The packet assembly request received from (1) to 4 (n) is stored in the packet assembly request storage units 7 (1) to 7 (n).
When the reference timing management unit 6 generates packet assembly timings at intervals of T seconds, the packet assembly request transmission unit 8
Read the packet assembly counter 9 and set it to the variable i,
At that timing, the packet assembly requests are taken out one by one in the stored order from the packet assembly request storage unit 7 (i),
It is transmitted to the packet assembly processing unit 2. Furthermore, the variable i
"1" is added, and when i = n, "1" is added to the variable i.
Is set and written in the packet assembly counter 9.

[0015]

As described above, the present invention manages the timings of requests for assembling a plurality of packets at the same time, so that the load on the CPU and the packet switch can be prevented from increasing.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an overall configuration of an embodiment of the present invention and a block configuration diagram showing a configuration of a packet activation timing correction unit included in this configuration diagram.

FIG. 2 is a timing chart showing the operation of a packet activation timing correction unit shown in FIG.

FIG. 3 is a block configuration diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Input Processing Section 2 Packet Assembly Processing Section 3 Packet Activation Timing Correction Section 4 Packet Activation Processing Section 5 Output Processing Section 6 Reference Timing Management Section 7 Packet Assembly Request Storage Section 8 Packet Assembly Request Transmission Section 9 Packet Assembly Counter

[Procedure amendment]

[Submission date] October 7, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a configuration of a packet activation timing correction unit according to the embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of a packet activation timing correction unit shown in FIG.

FIG. 4 is a block configuration diagram showing a configuration of a conventional example.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 4]

[Figure 3]

Claims (2)

[Claims] 1. A packet activation processing unit that receives a packet activation signal corresponding to each packet for each packet and generates a packet assembly request signal according to the packet activation signal, and a timing at which this packet assembly request signal is given. In a packet transmission device equipped with a packet assembly processing unit that assembles the packet, a reference timing management unit that independently generates a reference timing at a fixed interval for each packet, and a packet assembly request signal are stored to generate a reference timing. A packet transmission device comprising a packet start timing correction unit that sometimes extracts a packet assembly request signal corresponding to the packet from the stored packet assembly request signal and provides the packet assembly processing unit with the packet start timing correction unit. .. 2. The packet activation timing correction unit is
A packet assembly request storage unit that stores a packet assembly request signal for each packet in the order received, a packet assembly counter that specifies a packet to be assembled when a reference timing is received, and a packet assembly request specified by this packet assembly counter. The packet transmission device according to claim 1, further comprising a packet assembly transmission unit that sequentially extracts the storage units from the storage unit and provides the packet assembly processing unit with the packet assembly transmission unit.