JPH03143100A - Sound field compensation device - Google Patents

Abstract

PURPOSE:To obtain a good sound field space for either of the right or the left position of a driving seat by using the effective sound generating means of a left channel for a right channel, and using the effective sound generating means of the right channel for the left channel. CONSTITUTION:When a low level signal is supplied from an initial set circuit 22 and a switch 23 is turned on, this means that this device 12 installed on a left-handled vehicle. Then, a coefficient data group CDn(R) is read out, and is transferred and written into the first channel area of a coefficient RAM 7. Further, a coefficient data group CDn(L) is read out, and is transferred and written into the second channeling area of the RAM 7. Also, a delay time data group DDn(R) is read out, and transferred and written into the first channel area of a delay time RAM 21, and a delay time data group DDn(L) is read out, and is transferred and written into the second channel area of the RAM 21. Thus, the good sound field space can be obtained at the driving seat position for a vehicle with a handle at either the left or the right position.

Description

TECHNICAL FIELD The present invention relates to a sound field correction device that performs sound field correction by adding a sound effect signal such as a reflected sound signal to an audio signal.

BACKGROUND ART There is a sound field correction device that performs sound field correction on an audio signal in order to obtain a good acoustic space, for example, a sense of presence, in a home or a vehicle interior. In such a sound field correction device, a sound effect signal such as a reflected sound signal is added to an audio signal output from an audio device such as a cassette deck. In other words, reproduced sound in which anti-η, I-sound, etc. are added in a pseudo manner to the direct sound is transmitted to the listener. Furthermore, in the case of stereo audio signals, sound effect signals are added to each audio signal in the left and right channels.

By the way, it is impossible for all passengers to be located at the center of the sound field in the vehicle interior. Therefore, characteristics such as the delay time of the sound effect signals of the left and right channels are usually determined so that the driver's seat position is at the center of the sound field. however,
There was a problem in that it needed to be compatible with not only right-hand drive vehicles but also left-hand drive vehicles.

Summary of the Invention [Object of the Invention] Therefore, an object of the present invention is to provide a sound field correction device that can obtain a good sound field space at the driver's seat position, regardless of whether the steering wheel is in the left or right position of the vehicle. be.

[Structure of the Invention] The sound field correction device according to the present invention generates a sound effect signal according to an audio signal of an input channel, and adds the sound effect signal to the audio signal of the input channel. The sound field correction device is equipped with a sound effect generating means, and includes a switching means for changing the sound effect generating means for the left channel to the right channel and changing the sound effect generating means for the right channel to the left channel in response to a switching command. It is characterized by having

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the in-vehicle sound field correction device which is an embodiment of the present invention shown in FIG. 3. A data bus 4 is connected to the input interface 3, and this data bus 4 is connected to a data memory 17 for temporarily storing a data group and one input of a multiplier 5. A buffer memory 6 for holding coefficient data is connected to the other input of the multiplier 5. A coefficient RAM 7 is connected to the buffer memory 6, and a RAM
7 stores a coefficient data group.

One piece of coefficient data is sequentially read from a group of coefficient data stored in RAM 7 in response to a timing signal from a sequence controller 10, which will be described later, and is supplied to buffer memory 6 and held therein. The coefficient data held in buffer memory 6 is supplied to multiplier 5. A
An LU (adder) 8 is provided to accumulate the calculation output of the multiplier 5, and one input is supplied with the calculation output of the multiplier 5, and the other input is connected to the data bus 4. A
Accumulator 9 is connected to the calculation output of LU8,
The output of accumulator 9 is connected to data bus 4. Connected to the data bus 4 is a memory control circuit 19 that controls data writing and reading from the external memory 18 . A delay time RAM 21 that stores a group of delay time data is connected to the memory control circuit 19, and the memory control circuit 19 controls the external memory 18 so as to delay the audio signal data by each delay time data stored in the delay time RAM 21. Writes and reads input audio signal data to and from the input audio signal.

Further, an output interface 11 is connected to the data bus 4, and a digital audio signal output from the output interface 11 is supplied to a D/A converter 13 via a digital filter 12. The D/A converter 13 outputs left and right channel audio signals.

A/D converter 1, interfaces 3 and 11, multiplier 5
, coefficient RAM 7, ALU 8, accumulator 9 and memory control circuit 19 are operated by sequence controller 10.
controlled by The sequence controller 10 operates according to a processing program written in the program memory 20 and also operates according to instructions from the microcomputer 14.

A keyboard 16 is connected to the microcomputer 14. Keyboard] 6 has sound field modes 1 and 6 with different sound field characteristics. A plurality of keys are provided for specifying any one of the plurality of sound field modes: sound field mode 2, etc., and the microcomputer 14 rewrites or rewrites the processing program according to the operation of these keys. Controls rewriting of coefficient data in RAM 7 and delay time data in RAM 21. Also, the microcomputer 14 has the first ID.
A J setting circuit 22 is provided. The initial setting circuit 22 includes a manually operated initial setting switch 23 and a resistor 24, and supplies a high level signal to the microcomputer 14 when the switch 23 is off, and supplies a low level signal when the switch 23 is on. The switch 23 is normally turned off when the present device is installed in a right-hand drive car, but when installed in a left-hand drive car, it is suddenly turned on by the user's operation.

Furthermore, the microcomputer 14 has an internal memory (not shown) consisting of a ROM that stores processing programs, coefficient data groups, and delay time data groups for each sound field mote.

In this configuration, the left and right channel audio signals supplied to the A/D converter 1 are converted into digital audio signal data at every predetermined sampling period, and are supplied to the data memory 7 via the interface 3 and stored therein. Ru. The sequence controller 10 controls the timing of reading data from the interface 3, the timing of selectively transferring data from the data memo 'J 17 to the multiplier 5, the timing of outputting each coefficient data from the RAM 7, and the timing of multiplication operation of the multiplier 5. , ALU
The timing of the addition operation of 8, the output timing of the accumulator 9, the timing of outputting the data of the calculation result from the interface 11, etc. are determined.

By taking these timings, the audio signal data input from the data memory 17 is read out and supplied to the memory control circuit 19 via the data bus 4. One memory control circuit sequentially writes the supplied signal data into the external memory 18. On the other hand, according to the timing signal from the sequence controller 10, the delay time RA
Delay time data is sequentially read out from M21, and when a delay time specified by the delay time data has elapsed, the signal data is sequentially read out by the memory control circuit 10. Each read signal data is supplied to the data memory 17 via the data bus 4 and sequentially stored as delayed signal data.

Further, the audio signal data stored in the data memory 17 or the delayed signal data obtained by the above-described data delay processing are sequentially read out and supplied to the multiplier 5. On the other hand, coefficient data is sequentially read from the RAM 7 and supplied to the buffer memory 6 where it is held. For example, coefficient data α1 from the buffer memory 6 and data d1 from the data memory 17 are supplied to the multiplier 5, and the multiplier 5 first calculates α1·dl. When this α1·d] is calculated, 0+αI ◆d is calculated in the ALU 8, and the result of the calculation is held in the accumulator 9. Next, when the coefficient data α2 is outputted from the buffer memory 6 and the data d2 is outputted from the data memory 17, the multiplier 5 calculates a2·dl, the accumulator 9 outputs α1·dl, and the ALU 8 calculates α1·dl. d1+α2·dl is calculated, and the result of the calculation is held in the accumulator 9. Sα0dε is calculated by repeating this data multiplication and addition process.

RAM7 and RAM21 each have a first memory area as a data storage area.
and a second channel area. R.A.M.
7, the addresses of the first channel area are determined, for example, from address 1 to address m (positive integer), and the address of the second channel area is determined from address m+1 to address 2m, as shown in FIG. The same applies to the RAM 21. In each of the first and second channel areas, data α1, . a2...
It is written as α,... When reading data, first, data is read out from the address with a small value in the first channel area according to the timing signal, and when all the data in the first channel is read out, data delay processing or data multiplication and addition processing for the left channel is performed. Next, data is read out from the second channel area according to the timing signal, and when all the data of the second channel is read out, the data delay processing or data multiplication and addition processing of the right channel is finished. It will become.

FIG. 3 shows an analog equivalent circuit that performs operations similar to those described above. In this circuit, the left and right channel input audio signals are fed to delay elements 31, 32. The delay elements 31 and 32 delay the input audio signals by a plurality of delay times and output the delayed signals. These delayed left and right channel audio signals and input audio signals are sent to a multiplier circuit 33. ．． 34 to generate the number of IE reflected sound signals. The multiplication circuit 33.34 includes a plurality of multipliers 331-3316.34t- which individually multiply the supplied input audio signal and each delayed audio signal by coefficients.
3416. The outputs of the multipliers 331 to 339 and the outputs of the multipliers 341Q to 3416 are connected to an adder 35. The reflected sound signals output from the multipliers 3410 to 3416 are added to form the left channel output audio signal subjected to sound field correction. Further, each output of the multipliers 341 to 349 and each output of the multipliers 3310 to 33I6 are connected to an adder 36, and in the adder 36, the multiplier 34
Multipliers 342 to 3
The reflected sound signals outputted from 49 and multipliers 3310 to 3316 are added to form a right channel output audio signal subjected to sound field correction.

Next, in the microcomputer 14, the coefficient data groups CDI(L) and CD2(L) for the left channel are stored in the internal memory as shown in FIG.
), . . . and the coefficient data group CD+ (R), CD2 (R), . . . for the right channel are stored, as well as the delay time data group D for the left channel.
D+ (L), DD2 (L), ... and delay time data group DD+ (R)D for the right channel
D2 (R), . . . are stored. This defines data for the left and right channels based on right-hand drive cars. Although not shown, processing programs PI, P2, . . . for each sound field mode are also stored in the internal memory.

The operation of writing these data into the RAMs 7 and 21 will be described below with reference to FIG.

When the sound field mode n (positive integer) is specified by the key operation from the keyboard 16, the microcomputer 14
First, the output is muted and the operation of the sequence controller 10 is stopped (step 41), the processing program P0 is read from the internal memory, and the read processing program Pn is transferred to the program memory 20 and written into the program memory 20 (step 41). Step 42). Next, it is determined whether the switch 23 is on or not (step 4).
3). This is determined by whether or not a high level signal is supplied from the initial setting circuit 22 as described above. If a high level signal is supplied, the switch 23 is off, which is the case if the device is installed in a right-hand drive vehicle. In this case, the coefficient data group CDn (L) is read out, transferred to the first channel area of the coefficient RAM 7 and written (step 44), and then the coefficient data group CDn (R
) is read out, transferred to the second channel area of RAM 7, and written (step 45). In addition, the delay time data group DDn (L) is read out and the delay time RAM 21
Further, the coefficient data group DDn (R) is read out and transferred to the second channel area of the RAM 21 and written (step 47).

On the other hand, if a low level signal is supplied from the initial setting circuit 22, the switch 23 is on, which is the case when the present device is installed in a left-hand drive vehicle.

In this case, the coefficient data group CDn (R) is read out, transferred to the first channel area of coefficient RAM 7, and written (step 48), and then the coefficient data group CDn
(L) is read out, transferred to the second channel area of the RAM 7, and written (step 49). Further, the delay time data group DDn (R) is read out, transferred to the first channel area of the RAM 21, and written (step 50);
Furthermore, the delay time data group DDn (L) is read out and R
It is transferred and written to the second channel area of A to 121 (step 51).

When the program and data are rewritten in this way, the mute state is divided by the angle q and the sequence controller 10 is commanded to start operation (step 52).

Therefore, when the switch 23 is off, that is, when this device is installed in a right-hand drive vehicle, the coefficient data group CDn (L) is used in the left channel data multiplication and addition processing, and the coefficient data group CDn (L) is used in the left channel data delay processing. The 0-interval data group DDn(L) is used. Coefficient data group CDn in right channel data multiplication and addition processing
(R) is used, and the delay time data group DDn (R) is used in the data delay processing of the right channel.

On the other hand, when the switch 23 is on, that is, when this device is installed in a left-hand drive vehicle, the coefficient data group CDn (R) is used in the left channel data multiplication and addition processing, and the coefficient data group CDn (R) is delayed in the left channel data delay processing. A time data group DDn (R) is used. Coefficient data group CDn in right channel data multiplication and addition processing
(L) is used, and the delay time data group DDn (L) is used in the data delay processing of the right channel.

In the above-mentioned embodiment, the coefficient data group and the delay time data group for the left and right channels are respectively stored in the internal memory, and the data group for both channels is stored in both the right-hand drive vehicle and the left-hand drive vehicle. They are read and used, but the coefficient data group and delay time data group for the left and right channels are duplicated and stored in internal memory as right-hand drive data and left-hand drive data so that the channel areas are exchanged and written to RAM 7 and 21. If the vehicle is a right-hand drive vehicle, the right-hand drive data may be read out and used, and if the vehicle is a left-hand drive vehicle, the left-hand drive data may be read out and used.

Effects of the Invention As described above, in the sound field correction device according to the present invention, the sound effect generating means for the left channel is used for the right channel, and the sound effect generating means for the right channel is used for the left channel, in response to a switching command. Therefore, regardless of whether the steering wheel is in the left or right position of the vehicle, it is possible to obtain a good sound field space at the driver's seat position.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a storage area of coefficient RAM in the device of FIG. 1, and FIG.
The figure is a circuit diagram showing an equivalent circuit that performs the same operation as the DSP in the device shown in Figure 1, Figure 4 is a diagram showing the data storage state of the internal memory of the microcomputer, and Figure 5 is the operation of the microcomputer. FIG. Explanation of symbols of main parts 2...DSP 10...Sequence controller 14...Microcomputer 22...Initial setting circuits 31, 32...Delay elements 33, 34...Multiplication circuit

Claims (2)

[Claims] (1) A sound field correction device equipped with sound effect generation means for the left channel and right channel that generates a sound effect signal according to the audio signal of the input channel and adds the sound effect signal to the audio signal of the input channel. And,
A sound field correction device comprising a switching means for switching the sound effect generating means for the left channel to the sound effect generating means for the right channel and switching the sound effect generating means for the right channel to the sound effect generating means for the left channel in response to a switching command. (2) Each of the sound effect generation means has a delay means for delaying the audio signal of the input channel by a delay time, and a multiplication means for multiplying the delayed audio signal by a coefficient to obtain the sound effect signal, and The switching means includes a storage means for storing data for the left channel and data for the right channel as data indicating the delay time and the coefficient, and reads out the data for the left channel from the storage means and performs the delay means and the multiplication for the left channel. and reads the data for the right channel from the storage means and supplies it to the delay means and the multiplication means of the right channel, reads the data for the right channel from the storage means in response to the switching command, and reads the data for the right channel from the storage means. supplying the data to the delay means and the multiplication means, reading data for the left channel from the storage means and supplying it to the delay means and the multiplication means of the right channel, and using the supplied data, the delay means and the multiplication means operate. The sound field correction device according to claim 1, characterized in that: