JPH0638275B2 - Digital signal processor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital signal processor (hereinafter referred to as a DSP).

BACKGROUND ART An audio signal processing device capable of performing sound field control for producing a reverberant sound or a realistic sensation in a concert hall or theater at home or in a car is known, for example, Japanese Patent Laid-Open No. 64-72651. It is shown in the official gazette. Such an audio signal processing device performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner.
SP is provided. The DSP includes arithmetic means for performing arithmetic operations such as four arithmetic operations, a data memory for storing audio signal data supplied to the arithmetic means, and a delay memory for delaying the signal data stored in the data memory. In the DSP, the signal data is transferred between the memories and from the memories to the arithmetic means in accordance with a predetermined program, and the arithmetic processing of the signal data can be repeatedly performed at high speed. The program is written in a rewritable program memory such as a RAM in the DSP, and the program is changed by a microcomputer outside the DSP every time the sound field mode is switched by an operation. That is, it is possible to create any acoustic space by changing the program.

Some DSPs have a plurality of input ports for digital signal input. For example, as shown in FIG. 2, a signal obtained by digitizing an analog audio signal from an analog audio signal source 1 such as a tuner by an A / D converter 2 is supplied to a first input port IN ₁ of a DSP 3 and a CD (compact) A digital audio signal from a digital audio signal source 4 such as a disc player is supplied to a second input port IN ₂ of the DSP 3 via a DIR (digital audio interface receiver) 5. Input registers 6 and 7 are provided in the first and second input ports IN ₁ and IN ₂ , respectively, and the supplied digital audio signal is sequentially held in the input register 6 or 7. The input registers 6 and 7 are connected to a common data bus 8. This data bus 8
Is connected to a data memory (not shown) of the arithmetic processing unit 9, and normally the digital signal data supplied to the DSP 3 is written in the data memory for arithmetic processing.

By the way, the signal data held in the input register 6 or 7 is transferred to an element such as a data memory according to the program written in the program memory. Therefore,
In the case where the input signal data held in the input register 6 is transferred to the data memory for arithmetic processing, and in the case where the input signal data held in the input register 7 is transferred to the data memory for the same arithmetic processing thereafter. Different programs must be used, and the programs must be transferred from the microcomputer and rewritten each time the input port for inputting the digital signal to be processed is switched. However, there is a problem that a memory having a large storage capacity is required in order to store a large number of programs in a memory such as a ROM in a microcomputer for each input port.

Further, the changeover switch 10 is connected to the first and second input port _IN 1, IN ₂ as shown in FIG. 3 as a conventional DSP, each input to the first and second input port _IN 1, IN ₂ Some digital signals are selectively supplied to the input register 6 by the change-over switch 10. The selective switching of the changeover switch 10 is performed in response to a command from the microcomputer.

However, in this DSP, it is not possible to simultaneously use two input ports of the first and second input ports IN ₁ and IN ₂ . Therefore, since one input port can normally handle only two channels of digital signals, there is a problem in that DSPs cannot be cascaded and two channels (for four channels) of digital signals cannot be simultaneously input and processed. there were.

SUMMARY OF THE INVENTION [Object of the Invention] An object of the present invention is to enable switching of input ports for inputting digital signals to be processed without storing programs in a memory in a microcomputer by the number of input ports, and a plurality of systems. Is to provide a DSP capable of processing the digital signals of

[Structure of the Invention] The DSP of the present invention is provided with a plurality of input ports to which digital signals to be processed are supplied, and a data bus provided for each of the input ports and holding the digital signals supplied to the input ports and having a common output. With an input register connected to
The SP is characterized by including switching means for selectively connecting the output of any one of the plurality of input ports to the one input register according to a control signal.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In the DSP as one embodiment of the present invention shown in FIG. ₁ , a digital audio signal is supplied from the A / D converter 2 to the first input port IN ₁ and the second input port IN ₁ is supplied.
_The digital audio signal is supplied to the ₂ from the DIR 5 as in the conventional case. A changeover switch 10 as a changeover unit is connected to the first input port IN ₁ ,
The input digital signal to the input port IN ₁ is supplied to the input register 6 via the changeover switch 10. The second
The input port IN ₂ is directly connected to the input register 7 and also connected to the changeover switch 10. The change-over switch 10 selectively relays the signal from either _{one of} the first and second input ports IN ₁ and IN ₂ to the input register 6 in response to a control signal held in a control register 21 described later.

The outputs of the input registers 6 and 7 are connected to the data bus 8. The data bus 8 is connected to one inputs of a data memory 11 for temporarily storing a data group and a multiplier 12 via a buffer memory 19. A coefficient memory 14 is connected to the other input of the multiplier 12 via a buffer memory 13, and a coefficient data group is stored in the coefficient memory 14.
One coefficient data is sequentially read from the coefficient data group stored in the coefficient memory 14 according to a timing signal from the sequence controller 20 described later, and the coefficient data is supplied to the buffer memory 13 and held therein. The coefficient data held in the buffer memory 13 is supplied to the multiplier 12. The ALU (adder) 15 is provided to accumulate the calculation output of the multiplier 12, and one input has the multiplier 1
5 of the calculated outputs are provided, the other being connected to the data bus 8. An accumulator 16 is connected to the calculation output of the ALU 15, and an output of the accumulator 16 is connected to the data bus 8. Further, output registers 17 and 18 are connected to the data bus 8. Output register 17,
Reference numeral 18 holds the signal data that has undergone arithmetic processing, and outputs the held data from the first and second output ports OUT ₁ and OUT ₂ .

Data memory 11, multiplier 12, coefficient memory 14, AL
The operation timing of data transfer and calculation between elements such as U15 and accumulator 16 is the sequence controller 2
Controlled by 0. The sequence controller 20 operates according to the processing program written in the program memory 30, and operates according to a command from the microcomputer 23. A control signal as a command from the microcomputer 23 is supplied to the above-mentioned control register 21 via the interface 22 and held therein.
The microcomputer 23 controls the rewriting of the processing program and the rewriting of the coefficient data in the coefficient memory 14 according to the key operation of the keyboard 24. The control register 21 has a plurality of holding bits whose contents to be held are predetermined respectively, and is used for synchronization between the input digital audio signal, the DSP 3 and the microcomputer 23 and the switch 10.
It is provided for exchanging information such as switching control.

The DSP 3 is further provided with elements such as a memory control circuit for controlling data writing and reading of an externally connected memory for creating delay data and a delay time memory for storing the delay time data group. It is not shown because it is not directly related to the present invention.

Further, the DIR 5 is provided to demodulate a digital signal that has been subjected to bi-phase modulation.

In such a configuration, the changeover switch 10 is normally in the state where the first input port IN ₁ is selected. This first
When the input port IN _{1 is} selected, the first input port IN ₁
The digital audio signal supplied from the A / D converter 2 is supplied as signal data to the input register 6 via the changeover switch 10. A program counter (not shown) operates from an initial value in synchronization with the signal data to the input register 6, and operation steps of the program are sequentially read from the program memory 30 and supplied to the sequence controller 30. If the program written in the program memory 30 has a command step for transferring the input signal data to the input register 6 to the data memory 11 and is the first program for performing a predetermined arithmetic processing, the transfer command step The sequence controller 30 generates an operation command signal in response to the signal, and the signal data held in the input register 6 is transferred to the data memory 11 in the data bus 8
And is written to a predetermined address.

As the predetermined arithmetic processing, for example, the first input port IN
_One input signal data is sequentially transferred to the data memory 11 and written therein, and the signal data stored in the data memory 11 is sequentially read out and supplied to the buffer memory 19 and held therein. On the other hand, the coefficient data is sequentially read from the coefficient memory 14, supplied to the buffer memory 13, and held therein. The coefficient data is supplied from the buffer memory 13 and the signal data is supplied from the buffer memory 19 to the multiplier 12, and the multiplier 12 multiplies them one after another. The value obtained by this multiplication is accumulated in the ALU 15 with the value up to the previous time (the value held in the accumulator 16), and the operation result is held in the accumulator 16.

When the first input port IN ₁ of the changeover switch 10 is selected, the first input port IN _{1 with} respect to the digital audio signal from the digital filter 5 supplied to the second input port IN ₂ is selected.
In the case where the same arithmetic processing as the program is performed, as in the conventional case, the program memory 30 has an instruction step for transferring the input signal data from the first program to the input register 7 to the data memory 11 to perform the predetermined arithmetic processing. It is necessary to rewrite to the second program of.

However, in the selected state of the first input port IN ₁ of the changeover switch 10, for example, when an input port changeover command signal is generated by operating a predetermined key of the keyboard 24, a new control signal is sent from the microcomputer 23 via the interface 22. It is supplied to a predetermined bit position (connected to the changeover switch 10) of the control register 21.
Therefore, the content held in the predetermined bit position of the control register 21 is inverted, for example, from logic "0" to "1". Thereby, the changeover switch 10 is switched to the selected state of the second input port IN ₂ . In the second input port IN ₂ selected state, the changeover switch 1 receives the digital audio signal from the DIR 5 supplied to the second input port IN ₂ as signal data.
It is supplied to the input register 6 via 0. Therefore, in this case, the signal data supplied to the second input port IN ₂ is supplied to the input register 6 and held therein. Therefore, if predetermined arithmetic processing is performed, it is the same as in the first input port IN ₁ selected state. It is sufficient that the program memory 30 stores the first program. That is, the program counter operates from the initial value in synchronization with the signal data from the second input port IN ₂ to the input register 6, and the operation steps of the first program are sequentially read from the program memory 30 to the sequence controller 20. Supplied. The sequence controller 20 generates an operation command signal in accordance with the transfer command step of the first program, and the signal data held in the input register 6 is transferred to the data memory 11 via the data bus 8 and written at a predetermined address. is there.

Next, the first input port IN1 and the second input port IN2
A case will be described in which the two digital signals respectively supplied to the above are simultaneously subjected to arithmetic processing.

In this case, for example, it has a command step of transferring the input data of the first input port IN1 to the data memory 11 and another command step of transferring the input data of the second input port IN2 to the data memory 11, The third program for performing the arithmetic processing of is written in the program memory 30 from the microcomputer 23 through the interface 22 as in the case of the first program.

Further, a control signal is supplied from the microcomputer 23 to a predetermined bit position of the control register 21 via the interface 22. As a result, the changeover switch 10 has the first
The input port IN1 is selected. First input port I
In the N1 selected state, the digital audio signal from the A / D converter 2 supplied to the first input port IN1 is input as signal data to the input register 6 via the changeover switch 10.
, And the digital audio signal from the DIR 5 supplied to the second input port IN2 is supplied to the input register 7 as signal data. Therefore, in this case, the first
The program counter operates from the initial value in synchronization with the signal data from the input port IN1 to the input register 6, and the operation steps of the third program are sequentially read from the program memory 30 and supplied to the sequence controller 20. The sequence controller 20 generates an operation command instruction signal in accordance with the transfer command step of the third program, and the signal data held in the input register 6 is transferred to the data memory 11 via the data bus 8 and written in a predetermined address. Similarly, the signal data held in the input register 7 is transferred to the data memory 11 via the data bus 8 and written in a different predetermined address.

The digital audio signal is a parallel data signal formed from a plurality of bits indicating audio information, clock bits, and left and right channel bits. The left and right channel bits indicate which of the left and right channels the audio information is, for example, the left channel has a logical "1" and the right channel has a logical "0". The left and right channel bits are supplied to the control register 21,
The program counter operates from the initial value in synchronization with the inversion of the left and right channel bits, for example, from logic "0" to "1", and the sequence controller 30 generates an operation command signal.

Further, in the above-described embodiment, the changeover switch 10 selectively relays and supplies to the input register 6 any one of the signals input to the first and second input ports IN ₁ and IN _2. However, any one of the signals input to the three or more input ports may be relayed to one input register.

As described above, in the DSP of the present invention, the output of any one of the plurality of input ports is selectively set to 1 according to the control signal.
Switching means is provided for connecting to the input register.
Therefore, the same processing as the arithmetic processing performed on the digital signal supplied to the first input port is performed on the digital signal supplied to the second input port without changing the program written therein. be able to.
As a result, the number of programs to be stored in the memory in the microcomputer can be reduced, so that a memory with a large storage capacity is not required and cost can be reduced. Further, since the number of times the program is rewritten in the DSP is reduced, there is an advantage that the processing load on the microcomputer side is reduced.

It is also possible to simultaneously perform arithmetic processing on two digital signals respectively supplied to the first and second input ports.
Use SP in cascade connection, 4 channels A /
Two output signals from the D converter can be simultaneously input and processed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing a conventional DSP. Description of symbols of main parts 3 ... DSP 6, 7 ... Input register 10 ... Changeover switch 21 ... Control register 23 ... Microcomputer

Claims (2)

[Claims] 1. A plurality of input ports to which digital signals to be processed are supplied, and an input register which is provided for each input port and holds the digital signals supplied to the input ports and whose outputs are connected to a common data bus. And a switching means for selectively connecting the output of any one of the plurality of input ports to one input register according to a control signal. . 2. A digital signal processor according to claim 1, further comprising a control register which holds a port switching command signal supplied from the outside as the control signal.