JPH0314330A - User data separating system for image decoder - Google Patents

Abstract

PURPOSE:To receive and separate data interrupting user data by providing an image decoder for decoding a coding image signal outputted from a buffer memory circuit for temporarily storing an image data signal separated with a selector circuit. CONSTITUTION:The subject user data separating system is provided with the selecting circuit 100 for separating receiving data 1 into an image data signal 5 and a user data signal 6 by a data switching signal indicating the reception of user data, the buffer memory circuit 101 for temporarily storing the separated image data signal 5, the buffer memory circuit 102 for temporarily storing the separated user data signal 6, a clock formation circuit 103 for generating a clock signal 7 for writing data in the circuits 101, 102 by a data switching signal 2, and the image decoder 104 for decoding a coded image signal 9 outputted from the circuit 101. In the case of receiving prescribed data used by a user within the fixed time, data obtained by interrupting user data in the image data can be separatively received.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an image decoding device, and in particular to a user data separation method for an image decoding device that receives image data and user-specific data at high speed by separating or switching them. It is related to.

[Conventional technology]

Conventionally, an image decoding device separates user data from image data multiplexed at a fixed ratio.

[Problem to be solved by the invention]

In the user data separation method of the conventional image decoding device described above, when the speed of the transmission path is slow, since emphasis is placed on image data, the usable ratio of user data decreases, making high-speed transmission of user data difficult. Sometimes. However, if other audio data is being multiplexed simultaneously, there is a need for high-speed transmission of user data.

[Means to solve the problem]

The user data separation method of the image decoding device of the present invention is as follows:
a select circuit that separates received data into an image data signal and a user data signal using a data switching signal indicating reception of user data; a first breadthreader memory circuit that temporarily stores the image data signal separated by the select circuit; a second buffer memory circuit that temporarily stores the user data signal separated by the select circuit; and a clock generator that generates a clock signal for writing data into the first and second buffer memory circuits using the data switching signal. and an image decoder that decodes the encoded image signal output from the first buffer memory circuit.

[For production]

In the present invention, when a user wants to receive specific data at a specific time, it is possible to receive and separate the data in which user data is mixed into the image data. Sometimes it stops transmitting image data and transmits user data.

〔Example〕

Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 100 is a select circuit that separates received data into an image expansion data signal and a user data signal in response to a data switching signal indicating reception of user data, and 101 is a buffer memory that temporarily stores the image data signal separated by this select circuit 100. 102 is a buffer memory circuit that temporarily stores the user data signal separated by the select circuit 100; 103 is a clock generation circuit that generates a clock signal for writing data into the buffer memory circuits 101 and 102 according to the data switching signal; , 104 is an image decoder that decodes the encoded image signal output from the buffer memory circuit 101.

Figure 2 is a time chart used to explain the operation of Figure 1.
(a) shows data switching signal 2, (b)
is the received data signal 1, (C) is the transmission path frame synchronization signal 4, (d) is the data input pit signal 12m, (e) is the user data write clock signal 8, and (f) is the image data write clock. Signal 7, (g) is the user data signal 6. (h) shows the picture data signal 5.

In FIG. 1, 3 indicates a transmission line clock signal, 9 indicates an encoded image signal, 10 indicates a decoded image signal, and 11 indicates a user data signal. In the embodiment shown in FIG. 1, each signal is a digital signal.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

The received data signal 1 (see FIG. 2(b)) is input to the select circuit 100, and the received data signal 1 is converted into an image by the data switching signal 2 (see FIG. 2(a)) indicating reception of user data. Separate into data signal 5 (see Figure 2 (h)) and user data signal 6 (see Figure 2 (g)),
Output. Then, the image data signal 5 is temporarily written into the buffer memory circuit 101 by the image data write clock signal 7 (see FIG. 2(f)), and the encoded image signal 9 is output. This encoded image signal 9 is input to an image decoder 102, which outputs a decoded image signal 10. Similarly, the user data signal 6 is temporarily written to the expander memory circuit 102 by the user data write clock signal 8 (see FIG. 2(.)), and the user data signal 11 is output.

Next, the data switching signal 2 indicating reception of user data, the transmission line clock signal 3, and the transmission line frame synchronization signal 4 (see FIG. 2(c) M2) are input to the clock generation circuit 103, The image data write clock signal 7 and the user data write clock signal 8 are outputted by the clock signal 7.

This will be further explained with reference to FIG. FIG. 3 is a block diagram showing an example of the configuration of the clock generation circuit 103 shown in FIG. 1.

In FIG. 3, the same reference numerals as in FIG. 1 indicate corresponding parts; 200 is a register circuit, 201 is an n counter circuit, and 202a, 202b is a gate circuit.

In the clock generation circuit 103 configured in this way, first, the data switching signal 2 is input to the register circuit 200K, and the timing is set using the transmission line frame synchronization signal 4.
A clock inhibit signal 13a is output, and the polarity is further inverted to produce a clock inhibit signal 13b. 1
In addition, the transmission line clock signal 3 is input to the n counter circuit 201 button and the AND gate circuits 202m and 202b. Then, the n counter circuit 201 resets the clock counter using the transmission path frame synchronization signal 4, and outputs the data inhibit signal 12 & (see FIG. 2(d)) for extracting the clock signal by the number n of user data. Output.

The polarity of the data inhibit signal 12a is inverted to form a data inhibit signal 12b.

Next, the clock inhibit signal 13m, the data inhibit signal 12b>, and the transmission line clock signal 3 are input to the AND gate circuit 202b, and the image data write clock signal T is output. Then, clock inhibit signal 13b, data inhibit signal 12 & transmission line clock signal 3ft and gate circuit 202a
and outputs the user data write clock signal 8.

〔Effect of the invention〕

As explained above, in the present invention, when a user uses the system to receive specific data at a specific time, it is possible to receive and separate data in which user data is inserted into image data. Additionally, when you want to send a large amount of data, you can stop the image data transmission and transmit the user data, allowing for faster and more efficient use, which has the effect of allowing the receiving side to efficiently separate data reception. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart for the operation shown in FIG. FIG. 2 is a block diagram illustrating an example. 100...Select circuit, 101. 102...
. . . Buffer memory circuit, 103 . . . Clock generation circuit, 104 . . . Image decoder. @Figure 3

Claims (1)

[Claims] a select circuit that separates received data into an image data signal and a user data signal based on a data switching signal indicating reception of user data; and a first buffer memory that temporarily stores the image data signal separated by the select circuit. a second buffer memory circuit that temporarily stores the user data signal separated by the select circuit; and a clock signal for writing data to the first and second buffer memory circuits that is connected to the data switching signal. 1. A user data separation method for an image decoding device, comprising: a clock generation circuit generated by the first buffer memory circuit; and an image decoder that decodes the encoded image signal output from the first buffer memory circuit.