JPH0447892A - User data multiplexing system for picture coder - Google Patents

Abstract

PURPOSE:To attain the efficient utilization of a transmission line at a high speed by selecting either a picture data signal or a user data signal and outputting the selected signal in response to a switching signal sent from a timing circuit. CONSTITUTION:When a user data transmission request signal 1 is inputted to a picture coder 100, the picture coder 100 makes refreshing. Moreover, the signal 1 is inputted to a clock generating circuit 102 and a timing circuit 104. The circuit 102 inputs transmission line clock signal 6 and a transmission line frame synchronizing signal 11 and outputs a picture data read clock signal 7 and a user data read clock signal 8 and also a data inhibit signal 12 according to the signal 1. The circuit 104 receives the signals 11, 12 and outputs a switching signal 13 in response to the signal 1. A picture data signal 9 and a user data 10 are inputted to a selector circuit 105, in which either the signal 9 or the signal 10 is selected by using the switching signal 13 and the result is outputted as a transmission data signal 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a user data multiplexing method for an image encoding device.

[Conventional technology]

In a user data multiplexing method of a conventional image encoding device, image data and user data are multiplexed at a fixed time ratio.

[Problem to be solved by the invention]

In the conventional method described above, when the transmission path speed is slow,
Since emphasis is placed on image data, the percentage of time that user data can be used must be reduced.High-speed transmission of user data is difficult, especially when multiplexing other audio data at the same time. The disadvantage is that it cannot be transmitted.

[Means to solve the problem]

The system of the present invention includes an image encoder that encodes an image signal according to a control signal indicating whether or not user data is to be transmitted, and a first buffer memory circuit that temporarily stores the image data signal encoded by the image encoder. a second buffer memory circuit that temporarily stores a user data signal; and a clock generation circuit that generates a clock signal indicating timing for reading data from the first and second buffer memory circuits in accordance with the control signal; a timing circuit that generates a switching signal indicating output switching timing between the image data signal and the user data signal in response to the control signal; and a select circuit that selects and outputs one of the user data signals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a signal timing diagram in this embodiment. Note that each signal in this embodiment is a digital signal.

The input image signal 2 is input to the image encoder 100, and the image encoder 100 encodes it into an encoded image signal 4 (
Figure 2 (C)) is output. The encoding timing of the image encoder 100 is controlled so that encoding starts when the data occupancy amount 5 stored in the buffer memory circuit 101 becomes less than a certain threshold value. The encoded image signal 4 is temporarily stored in a buffer memory circuit 101, and is output as an image transmission data signal 9 when a read clock signal 7 is input. The user data signal 3 is temporarily stored in the buffer memory circuit 103, and is output as the user transmission data signal 10 when the read clock signal 8 is input.

When the user's data transmission request signal 1 is input to the image encoder 100, the image encoder 100 performs a refresh operation. Further, the data transmission request signal 1 is input to the clock generation circuit 102 and the timing circuit 104.

The clock generation circuit 102 inputs the transmission line clock signal 6 and the transmission line frame synchronization signal 11, and generates the image data readout clock signal 7 according to the data transmission request signal 1.
, a user data read clock signal 8, and a data inhibit signal 12.

In the timing circuit 104, the transmission line frame synchronization signal 1
and a data input signal 12, and outputs a switching signal 13 in response to the data transmission request signal 1.

Image data signal 9 and user data 10 are input to selector circuit 105, and either image transmission data signal 9 or user transmission data signal 10 is selected by switching signal 13 and output as transmission data signal 14.

FIG. 3 is a block diagram showing an example of the configuration of the clock generation circuit 102 of this embodiment. In the figure, data transmission request signal 1 is input to register circuit 200, and register circuit 2
00 takes timing with the transmission line frame synchronization signal 11, outputs a clock inhibit signal 15a, and further inverts the polarity to produce a clock inhibit signal 15b.

Transmission line clock signal 6 is input to n counter circuit 201 and AND gate circuits 202a and 202b. The n counter circuit 201 resets the counter using the transmission line frame synchronization signal 11, and outputs a user data inhibit signal 12a for extracting clock signals corresponding to the number n of user data. The user data inhibit signal 12a has its polarity inverted and is output as the data inhibit signal 12 from the clock generation circuit 102. The first clock inhibit signal 15a, the data inhibit signal 12, and the transmission line clock signal 6 are input to the AND gate circuit 202b, and the read clock signal 7 for image data is output. Second clock inhibit signal 15b and user data inhibit signal 12a
and the transmission line clock signal 6 by the AND gate circuit 202a.
and read clock signal 8 for user data.
output.

〔Effect of the invention〕

As described above, in the present invention, when a user uses the data to transmit data at a specific time, by requesting data transmission, user data can be inserted into image data and multiplexed transmission can be performed. Furthermore, when it is desired to transmit a large amount of data, transmission of the image data is stopped and user data is transmitted, thereby making it possible to use the transmission path efficiently and at high speed. Note that when image data is stopped in this manner, image frames are dropped frame by frame, so by keeping the refresh state until the transmission of user data is completed, transmission of image data can be promptly resumed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a signal timing diagram in one embodiment of the present invention, and FIG. 3 is a configuration example of the clock generation circuit 102 of the embodiment of the present invention. FIG. 1... Data transmission request signal, 2... Image signal, 3.
・. User data signal, 4...Encoded image signal, 5...
・Data occupancy, 6...Transmission line clock signal, 7, 8
. . . Read clock signal, 9 . . . Image transmission data signal, 10 . . . User transmission data signal, 11 .
Transmission path frame synchronization signal, 12... Data inhibit signal, 12a... User data inhibit signal, 13... Switching signal, 14... Transmission data signal, 1
5a. 15b...Clock in hipit signal, 100...
Image encoder, 101, 103...Buffer memory circuit, 102...Clock generation circuit, 104...Timing circuit, 105...Select circuit, 200...Register circuit, 201...N counter circuit , 202a,
202b...AND gate circuit.

Claims (1)

[Claims] an image encoder that encodes an image signal in accordance with a control signal indicating whether or not to transmit user data; a first buffer memory circuit that temporarily stores the image data signal encoded by the image encoder; a second buffer memory circuit for temporarily storing data; a clock generation circuit that generates a clock signal indicating timing for reading data from the first and second buffer memory circuits in response to the control signal; a timing circuit that generates a switching signal indicating output switching timing between the image data signal and the user data signal; and a timing circuit that generates a switching signal indicating output switching timing between the image data signal and the user data signal; A user data multiplexing method for an image encoding device, comprising a select circuit that selects and outputs one of the signals.