JPH0314367B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pulse generation circuit, and more particularly to a pulse generation circuit suitable for generating drive pulses for a television camera using a solid-state image sensor.

[Background of the invention]

A MOS solid-state image sensor has a light-receiving section consisting of photodiodes arranged in a matrix, and by switching vertical and horizontal readout switches connected to the photodiodes in an orderly manner, optical signals are sequentially converted into time-series signals. It's starting to read out. In this case, the vertical and horizontal readout switches are opened and closed by the output pulses of the vertical and horizontal shift registers built into the solid-state image sensor.
In order to operate the horizontal shift register, two-phase vertical clock pulses and vertical start pulses, and two-phase horizontal clock pulses and horizontal start pulses are required.

In addition, blanking pulses, horizontal and vertical synchronization signals, etc. are also required to convert the output signal of the solid-state image sensor into a television signal.

Conventionally, these pulses are generated by several M by an oscillator circuit.
Various necessary pulses were obtained by generating a high frequency pulse of Hz, dividing the frequency of this pulse to a predetermined frequency using a frequency dividing circuit, and combining the output pulses of each stage of the frequency dividing circuit using a logic circuit.

Incidentally, in conventional solid-state cameras, synchronous noise that appears in the video output has been a major problem, but in the present invention, the source of the synchronous noise is a drive pulse generator consisting of a combination of the above-mentioned frequency dividing circuit and logic circuit. He noticed this problem in the circuit, and proposed a new configuration of a drive circuit that solved this problem in Utility Application No. 138412-1983.

In other words, if a method is adopted in which an oscillator circuit generates high-frequency pulses and a frequency divider circuit (counter circuit) is used to reduce the pulses to a predetermined low frequency, the pulse noise generated at each stage of the frequency divider circuit will be transmitted to the power supply line. Noise pulses, particularly from the horizontal shift register side, enter the output signal line through the ground line, ground line, or electrostatic coupling, and appear as vertical striped noise on the screen. The feature of the drive circuit of the above-mentioned application that solves this problem is that a first oscillator generates a pulse at a horizontal synchronous frequency, and a horizontal clock pulse synchronized with this is generated by a second oscillator, thereby generating the necessary pulses for the horizontal soft register. is created without using a divider circuit, and on the other hand,
On the vertical register side, where periodic noise does not affect the screen, a frequency divider circuit is used to generate pulses of the desired frequency from high-frequency oscillation pulses.

The first part about the main part of this drive pollus generation circuit.
To further explain with reference to the drawings, first, the oscillator 34 oscillates the same horizontal period frequency to obtain the horizontal synchronizing pulse 16. The horizontal sync pulse 16 is used to synchronize the horizontal cross pulse generator 35. The output 25 of the horizontal clock pulse generator together with the pulse 27 generated by the delay circuit 36 and pulse width control circuit 37 becomes a two-phase horizontal clock pulse.

The horizontal synchronizing pulse 16 is also applied to a pulse width control circuit 38 and a horizontal blanking pulse generation circuit 39.

The output pulse of the pulse width control circuit 38 is combined with the horizontal synchronization pulse 16 in a logic circuit 40 to form a horizontal synchronization signal (H.SYNC pulse) 20. H・
SYNC pulse 20 also becomes the clock pulse that drives the vertical shift register.

In addition to being used as a vertical clock pulse, the horizontal blanking pulse 21 is combined with a horizontal clock pulse 25 in a horizontal input pulse generation circuit 41 to form a horizontal input pulse 29.

The pulse 21 also operates a counter circuit 42 and logic circuits 43 and 44, which generate a vertical input pulse 30 and a composite blanking signal. Further, the vertical synchronization signal generation circuit 46 generates a composite synchronization signal together with the logic circuit 45.

However, although the conventional drive pulse generation circuit shown in FIG. 1 can eliminate synchronous noise, there is a problem with the temperature stability of the horizontal clock pulse generation circuit 35.
The oscillation frequency fluctuated by several percent with a temperature change of 60°C. In normal oscillation circuits, temperature stability is achieved by using a crystal resonator, but a crystal cannot be used in a circuit that synchronizes with a horizontal synchronization signal and always performs synchronous oscillation with the same phase.

[Purpose of the invention]

The present invention was made in response to the above reasons, and aims to improve the temperature characteristics of an oscillation circuit that always starts oscillation at the same phase in synchronization with a trigger pulse, and is suitable for a drive pulse generation circuit for a solid-state image sensor. shall be.

[Embodiments of the invention]

FIG. 2 shows one embodiment of an oscillator circuit according to the invention, which corresponds to circuit 35 in FIG.

In the figure, 50 is an oscillator that starts oscillating in synchronization with the trigger pulse (horizontal synchronization pulse) 16 and with the same phase.For example, as shown in Figure 3, it uses a Schmitt circuit S, and its oscillation frequency is It can be controlled by voltage (voltage at terminal C).
51 is a frequency dividing circuit (counter circuit) for dividing the output pulse of the oscillator 50 into 1/m.

As already mentioned in the explanation of the background of the invention, the pulses generated in the frequency dividing circuit are superimposed on the video signal and become a noise source that degrades the screen. Therefore, in the circuit of the present invention, the operation of the frequency dividing circuit 51 is flipped. - The frequency dividing circuit is controlled by the flop circuit 54 so that it operates only during the horizontal blanking period when no video output occurs.

That is, the flip-flop circuit 54 is set by the horizontal synchronizing pulse 16, and the operation command signal Q is applied to the frequency dividing circuit 51 only during the setting period. The frequency divider circuit 51 thereby counts input pulses from the oscillator 50, and resets the flip-flop 54 with an output pulse when m pulses are counted within the horizontal blanking period.

Figure 4 shows the waveforms of each part of the circuit in Figure 2.
6 is a trigger pulse synchronized with the horizontal synchronization signal, 25
is the horizontal clock pulse produced by oscillator 50, 5
1S is an output pulse of the frequency dividing circuit 51. Also,
Q is the output pulse of the flip-flop circuit 54, and this pulse width is equivalent to m crop pulses 25. When the frequency of the clock pulse 25 changes due to temperature or the like, the pulse width of the output pulse Q of the flip-flop also changes.

Therefore, when the output pulse Q of the flip-flop circuit 54 is integrated by the integrating circuit 52, its DC level becomes proportional to the frequency of the oscillator 50. In the circuit of the present invention, the output of the integrating circuit 52 is input to the differential amplifier circuit 53 and compared with a reference voltage 55, and the power supply voltage of the oscillator 50 is controlled with an output voltage proportional to the difference between the two.

As is clear from the above embodiments, according to the present invention, even if the frequency of the output pulse 25 of the oscillator 50 fluctuates, this is automatically corrected and stable operation is achieved without causing synchronous noise. be able to.

In the above embodiment, the output pulse Q of the flip-flop circuit 54 was used as the pulse for detecting the DC level, but instead of the pulse Q, the output pulse Q of the frequency dividing circuit 5 was used.
One output pulse 51S may be used. Further, the counter circuit 51 generates horizontal flanking pulses by counting the clock pulses 25, and the pulses of various pulse widths generated in the process can be used for the above-mentioned DC detection, and any pulse width can be used as a standard. By selecting the voltage 55, the oscillator 50 can be caused to oscillate at a desired frequency.

In addition, as shown in Figure 5, the pulse for DC component detection is
If 60 V _OL , V _OH Dorito, etc. are a problem,
For example, as shown in FIG. 6, the output 68 of a reference voltage circuit consisting of a transistor 61 and resistors 62 and 63
The output 69 of a DC component detection circuit consisting of a transistor 64, resistors 65 and 66, and a capacitor 67 may be applied to the differential amplifier 53, respectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one example of a drive pulse generation circuit for a solid-state image sensor, and FIG. 2 is a block diagram of an example of a pulse generation circuit improved according to the present invention, which corresponds to the pulse oscillation circuit 35 in the drive pulse generation circuit described above. 3 is a diagram showing an example of the oscillator 50 in the circuit shown in FIG. 2, FIG. 4 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 2, and FIG. FIG. 6 is a signal waveform diagram and a circuit diagram for explaining a modification of the present invention. In FIG. 2, 50 is an oscillator, 51 is a frequency dividing circuit, 52 is an integrating circuit, 53 is a differential amplifier, and 54 is a flip-flop circuit.

Claims (1)

[Claims] 1. A pulse oscillator that oscillates in synchronization with a trigger pulse, and a counter circuit that periodically operates by a predetermined number of coefficients on the output pulses of the pulse oscillator.
A pulse generating circuit comprising means for outputting a DC voltage proportional to a coefficient operation period of the counter circuit, and means for controlling the operation of the pulse oscillator only within a horizontal blanking period in accordance with the DC voltage.