JPH03144694A - Address generating device for digital image display - Google Patents

Abstract

PURPOSE:To make a display with the high degree of freedom by converting parameters by using tables and allowing the tables themselves to be rewritten according to a desired display state. CONSTITUTION:When a CPU writes table data in an unread side between the look-up tables 9a and 9b, an address switching selector part 7 and a data switching selector part 11 are switched. Therefore, the look-up tables 9a and 9b to be read are switched and a table having fresh contents is referred to, thereby making a fresh display. Thus, the contents of the look-up tables 9a and 9b are easily switched when needed. Consequently, various free expressions are obtained on a CRT without adding nor altering circuits.

Description

[Detailed description of the invention] [Industrial application field] The present invention (when displaying image data on a CRT or the like,
The present invention relates to a digital image display address generation device used in an image display device that converts and displays images at arbitrary positions, angles, and sizes.

[Prior Art] Conventionally, image data created by an image creation device such as a television camera or CAD is stored in an image memory, and the image data is displayed at an arbitrary position on a CRT, or rotated, enlarged, or reduced.・Rusk scan type image display devices that can display images with left and right inversion are known.

Processing such as movement, rotation, enlargement, reduction, and horizontal reversal is generally performed by affine transformation in terms of calculation. This affine transformation is expressed as the following formulas (1) and (2). This formula is realized in a circuit and the display coordinates (x, y
), calculate the reading coordinates (X, Y), read the display data from the coordinates (X, Y) on the memory, and
Displayed at display coordinates (x, y) on RT.

×=a×+by ten α...(1) Y=cx+dy+β...(2) As an example, the circuit shown in FIG. 0).

This circuit is a multiplication circuit 100, 102 .
104 and 106 are provided, and a screen horizontal address counter 1 is provided.
08 coordinate value X, coordinate value y of the screen vertical address counter 110, constant values a and b from the CPU (not shown)
, c, d, a・x, b-y, c-x
, dy are multiplied, and then the adder circuits 112 and 114 add the output values of the multiplier circuits 100 and 102 or 104 and 106 to obtain the coordinate value X for image memory access,
It is outputting Y.

Another device includes an up/down counter that counts addresses based on a clock signal for counting display coordinates (Japanese Patent Laid-Open No. 144790/1982).

This is to switch the counting direction of the 20 counter between forward and reverse according to the on/off of the reverse command signal, and to display the image upside down and/or left and right. It is something to do.

[Problems to be Solved by the Invention] However, in the former case that uses a multiplication circuit, the multiplication process takes an extremely long time, and furthermore, it is not always processed in a constant time, so other processes, For example, it is difficult to balance this with the process of writing new image data into the image memory, and there is a risk that the entire display process will not proceed smoothly. Moreover, the circuit itself was large and required a lot of storage space.

Furthermore, when an up/down counter whose counting direction can be changed is used, as in the latter case, the processing time is short and constant. However, processing other than position reversal, e.g.
This is not possible without changing or adding to the processing circuit itself.

Therefore, if left as is, only very limited display can be performed, resulting in a display device with a very low degree of freedom. Furthermore, if a large number of display formats are to be realized, it is necessary to provide a number of processing circuits corresponding to each display format, which results in an increase in the size and cost of the device.

The present invention has been made for the purpose of solving the above-mentioned problem M.

[Means for Solving the Problems] The present invention has been made to solve the above problems.As illustrated in FIG. Used in a digital image display device that reads image data of an address and sequentially displays it on a two-dimensional display device M2,
The address generation device that outputs the above-mentioned address includes a parameter generation means M3 that generates a two-dimensional parameter indicating a display position of the two-dimensional display device M2, and a first table M based on a first parameter among the two-dimensional parameters.
4, the first conversion means M5 outputs the first conversion value.
And, based on the second parameter among the two-dimensional parameters above,
a second conversion means M7 that outputs a second conversion value with reference to a second table M6; and determining a read address for the image memory M1 by adding or subtracting the first conversion value and the second conversion value. Addition/subtraction means M8 for calculating at least one parameter
An address generating device for digital image display characterized by comprising: and table changing means M for rewriting the first table M4 and the second table M6 according to a desired display state.

[Operation] If the parameter generation means M31 & orthogonal coordinates,
Output the values of parameter X and parameter y.

These x and y correspond to the scanning position of the two-dimensional display device (for example, CRT) M2.

The first conversion means M5 refers to the first table M4 based on the value of the first parameter, for example parameter X. 1st
In the table M4, values corresponding to the calculated values of a*x explained in the conventional example have already been calculated and written in ascending or descending order of x.

Therefore, the calculated value stored at the position of X can be read out without performing multiplication.12 A.x can be obtained as the first converted value. Similarly, the second conversion means M7 also refers to the second table M6 based on the second parameter, for example, the parameter y ('L), and b-y as the second conversion value is determined without multiplication calculation.

This first. The second conversion value (Y) is added or subtracted by the addition/subtraction means M8. It is added when the above formula (1) or (2) is followed. This allows at least one reading address, e.g. Express it in coordinates (Dai) The address
S owns two first tables M4, and the second conversion means M7
owns two second tables M6, each has two conversion values (for example, 1.i a-x, c-x and b・y
, dy) may be obtained, and the addition/subtraction means M8 may perform two additions and subtractions (for example, ax+by and cx+dy) to obtain the two addresses X and Y.

In this way, each conversion means MS, M7 only performs reading of table values, and other calculations are carried out by the addition/subtraction means M.
8, the reading process from the image memory M1 is completed in a short and constant time.

[Embodiment] Next, a preferred embodiment of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing an embodiment of the address generation device for digital image display of the present invention. FIG. 3 shows an example of the configuration of a digital image display device using the address generation device 1. In FIG.

This address generation device 1 includes a main unit 1, an address counter section (corresponding to parameter generation means) 3, a window generation circuit 5, an address switching selector section 7, a lookup table section 9, a data switching selector section 11, and an addition section (addition/subtraction). (corresponding to means) consists of 13 pieces. Also, the digital image display device 1, the address generation device 1, the CPU (corresponding to the table changing means) 14, and the timing controller 15.
, sequential address generation circuit 17, switching circuit 19, image memory 21 . TV camera 23, A/D converter 25, D/A
Converter 27 and CRT (corresponds to two-dimensional display device) 2
It consists of one.

Address counter section 31 companies Three types of clock signals from the timing controller 15 cause the CRT29
The coordinates x, y corresponding to the display scan position on the screen of
X address counter 3 that counts and outputs each
It is equipped with a and y address counters 3b.

Horizontal clock pulse signals corresponding to scanning in the above three types of clock signals (front screen horizontal Cx) direction, screen vertical (
y) A vertical clock pulse signal corresponding to scanning in the direction, and a frame clock pulse signal representing a scan break for each screen.

X address counter 3a (upper) Inputs the horizontal clock pulse signal and the vertical clock pulse signal, counts up in synchronization with the horizontal clock pulse, and is cleared at the falling edge of the vertical clock pulse.

Y address counter 3bli Inputs the vertical clock pulse signal and the frame clock pulse signal, counts up in synchronization with the vertical clock pulse, and is cleared at the falling edge of the frame clock pulse. Therefore, the count value of the X address counter 3a indicates the X coordinate position of the scan, and the count value of the Y address counter 3b indicates the X coordinate position of the scan.

Window generation circuit 5 (friend) above count value x.

Based on y, the window is specified as described later.

The address switching selector section 7 (includes a first selector 7a and a second selector 7b).
, 7bl, each of the combinations of the count value x+V from the address counter section 3 and the window designation signal from the window generation circuit 5, and the combination of the LUT address signal and write control signal from the CPU 14. It is selected and transmitted to the lookup table unit 9. In this selection, another combination is selected for the two selectors 7a and 7b based on a UT (look-up table) selection signal from the CPU 14.

The lookup table section 9 includes a first lookup table memory 9a (corresponding to the first conversion means and the second conversion means) and a second lookup table memory 9b (corresponding to the first conversion means and the second conversion means). It is equipped. Since selectors 7g and 7b select different combinations,
In these two lookup table memories 9a and 9b,
One of them is set for reading, and the other is set for writing. For reading and writing, the CPU 14
It is replaced every time any table memory is rewritten by . Table contents (upper) In this example, it is set as a table for affine transformation. That is,
A table is provided that associates the values of the x address and y address with the numerical values necessary for affine transformation.

Affine transformation can be expressed as the following equation.

X=f + (X)+f2 (y) ... (
3) Y= f 3 (x) + f a (y)
-(4) Table contents (Yoko fl, f2
．． f3. This corresponds to f4.

For example, if the screen of the CRT 29 is 400 dots x 200 dots, in the case of horizontally inverted display, -for example, f, (x) = -x + 399. f2(y) ==
Set O, f 3 (x) = O, f 4 (y) ``y.The corresponding table fly f2 + f
3+f4m As shown in FIGS. 4(a) to (d).

Regarding the (U expansion, reduction, rotation, etc., the affine transformation 1 is obtained, so fl (x), f2 (y),
Set f3 (x) and fa (y) appropriately, and
By pre-calculating the multi-values according to the table fl+f2
It may be formed as +f3+f4.

This lookup table section 9 (consisting of iRAM) is rewritable and can be rewritten into a corresponding table depending on the desired display.

Also, if windows are set (dai), each table f+, f2. f3.
f4 is provided, and each time the window changes, a table corresponding to the window is selected and used.

The data switching selector unit 11 includes a first selector 11a and a second selector llb. 1st selector lla
is for selecting which memory, the first lookup table memory 9a or the second lookup table memory 9b, to write data from the CPU 14, and is selectively controlled by the above-mentioned UT selection signal. Second
The selector llb selects which of the first lookup table memory 9a and the second lookup table memory 9b the value obtained from is to be output to the adder 3 side. Selection is controlled by a selection signal. The first selector lla and second selector llb select different look-up table memories so that write and read accesses do not overlap with one memory.

The adder 13 includes a first adder 13a and a second adder 13b. The horizontal address x in the image memory 21 is calculated from the sum of fl(X) and f2(y) read from either of the two lookup table memories 9b. Further, the second adder 13b executes the addition according to the above equation (4), and the second adder 13b executes the addition of the above formula (4), and the first lookup table memory 9
From the sum of f3(X) and f4(y) read from either a or the second lookup table memory 9b,
The vertical address Y in the image memory 2 is calculated.

Sequential address generation circuit 17 (which performs the same function as the address counter section 3 described above,
ffl, and are output in order in correspondence with the scanning position of the CRT 29. Therefore, this circuit 17 does not need to be provided independently, and the output of the address counter section 3 may be used as is.

The switching circuit 19 switches between the arbitrary address signal of the address generation device 1 and the sequential address signal of the sequential address generation circuit 17 according to the high level and low level of the horizontal clock from the timing controller 15, and outputs the signal to the image memory 21. are doing. When the horizontal clock is at a high level, address signals are sequentially output, and when the horizontal clock is at a low level, an arbitrary address signal is output.

This horizontal clock is also output to the image memory 21, and when it is at a high level, the image memory 21 is put into a writing state, and when it is at a low level, it is put into a reading state. Therefore, each time the level becomes high, image data from the television camera 23 is written one dot at a time to the image memory 21 (starting from the first memory address). Image data is read from the address on the image memory 21 determined by the selected table f, , +2. +3.f, and displayed at the current scan position of the CRT 29.

Next, details of the window generation circuit 5 will be explained. As shown in FIG. 5, window generation circuit 51; jxX window table 5a1. y window table 5b-
1, a NAND processing section 5cm1, and a priority encoder 5cl-1.

As shown in FIG. 6, the X window table 5a-1 and the y window table 5b-111 are tables set with the number of bytes corresponding to the number of display dots on the CRT 29, and the If the number of dots N× is 400, it is formed on a memory of 400 bytes (1 byte=8 bits). The number Ny of dots in the vertical direction of the y window table 5b-t is 200.
If so, it is formed on 200 bytes of memory.

Bits O-7 of each byte represent 8 windows,
In each bit array, the "1" part corresponds to the part where the window is open. The highest priority is window O, followed by window 1. 2. 3゜4, 5.
6. 7 and the priority is getting lower.

One byte (8 bits) of each corresponding position is read from the window tables 5a-1, 5b-1 according to the x and y values from the address counter section 3 and output to the &NAND processing section 5cm1.

The NAND processing unit 5cm1 is equipped with eight NAND circuits corresponding to the number of bits in one byte, and performs NAND calculations for each bit on the signals from the respective tables 5a-1 and 5b-1. ing. The result is input to the priority encoder 5d-1.

The priority encoder 5d-1 is a logic circuit that outputs the bit position that is the first "O" when viewed from the bit O side of this 1-byte data, representing it as 3 bits (
For example (e. Priority encoder 5N74148 manufactured by Texas Instruments, etc.).

The relationship between the input and output is as shown in Table 1.

In Table 1, the input bits are the upper bits on the left and the lower bits on the right, indicating that rXJ may be i roJ or "1".

For example, the 8 bits obtained from the EX window table 5a-1 are roOOOOOOOOJ, and the 8 bits obtained from the y window table 5b-1 are [)000.
1 at the point Pi-1 (see Figure 6), which is 0000J.
The output of the AND processing unit 5C-1 is "11111111", and based on Table 1, "0" is output. "0" specifies window O. Therefore, the contents of the upper window ○ will be displayed at the x and y positions.

The 8 bits obtained from the x window table 5a-1 are rl 0000110J, and the 8 bits obtained from the y window table 5b-i are "0O000110J.
At point P1-2, the output of the NAND processing unit 5cm1 becomes rlllllooIJ, which specifies window 1.

The 8 bits obtained from the x window table 5a-1 are "rl 0000100", and the 8 bits obtained from the y window table 5b-1 are "0OOOO110".
At point PI-3, the output of the NAND processing unit 5cm1 becomes rlllllollJ.

The priority encoder 5d-1 outputs the "2" table. This will specify window 2.

Furthermore, the 8 bits obtained from the X window table 5a-1 are rl 0OOOOOOJ, and the 8 bits obtained from the y window table 5b-1 are "1000000".
1 at point PI-4 which is 0J NAND processing section 5cm1
The output of is rollllllllJ. Priority encoder 5d-1 outputs "7". This will specify window 7.

When this window number is output to the lookup table unit 9 by the selectors 7a and 7b, each table f+, f2 .
f3. From L, the table for the corresponding window is selected.

It will be used to find Y. That is, each table f+, f2. f3. fa stores a composite number of tables (e.g. 8) depending on the window, and the one selected depending on the window is
There are four tables shown in FIGS. 4(a) to 4(d).

FIG. 4 shows that a window to be horizontally reversed is selected.

In the window generation circuit 5 described above, each window is displayed as a rectangle, but the window generation circuit 5 shown in FIG.
-2 (f), it is also possible to create a cross-shaped window as shown in FIG.

Here, the X window table 5a-2, the y window table 5b-2, and the priority encoder 5d
-2 is the same as the example shown in FIG. 5, except that the logic circuit for each bit is a NOR processing section 5C-2. The NOR processing unit 5C-2 is equipped with eight NOR circuits,
NOR calculation is performed for each bit of the signals from each table 5a-2, 5b-2. The result is input to the priority encoder 5d-2.

For example, [8 obtained from the 1X window table 5a-2
The bit is roooooooooJ, and the 8 bits obtained from the y window table 5b-2 are “○oooooo
At point P2-1 (see FIG. 8) where the output is "o○", the output of the NOR processing unit 5C-2 becomes "11111111J,"
Based on Table 1, "O" is output, and as a result, the contents of window O are displayed at the scan position at that time.

The 8 bits obtained from the
At point P2-2 which is 00J (Yo) NOR processing part 5cm2
The output will be rol 111001J, and the contents of window 1 will be displayed from Table 1.

On the other hand, the 8 bits obtained from the X window table 5a-2 are ro OOOOOOOOJ, and the 8 bits obtained from the y window table 5b-2 are rl 0000.
000'' at point P2-3, the NOR processing section is 5 cm2
The output is rollllllllJ, and the contents of window 7 from Table 1 are displayed.

Due to the configuration of the digital image display device as described above, any display including window display is possible without performing multiplication during display, depending on how the tables in the lookup table memories 9a and 9b are set. Become.

Next, the processing of the CPLJ 14 for rewriting the contents of the table will be explained.

As shown in the flowchart of FIG. 9, the processing of the CPU 14 is performed by an instruction from an operator (for example, a car driver) or automatically (1). The lookup table data corresponding to the determined instruction is written to the lookup table memory that is not currently being read out of the two lookup table memories 9a and 9b (step 12o). The CPU 14 selects the lookup table data corresponding to this instruction from various lookup table groups pre-stored in a storage device (not shown) and writes it, or the Based on CPU
14 may calculate and create a lookup table and write it.

The LUT selection signal is then switched (step 130
). As a result, X and Y are calculated using the values found in the lookup table written just before. Next, move on to other processing.

In the digital image display address generation device configured as described above, when the address counter section 3 outputs x and y values corresponding to the scan position of the CRT 29,
The window generation circuit 5 determines a window number based on the x and y values, and the lookup table corresponding to that window number is stored in one of the lookup table memories 9.
It is specified from the table group in a and 9b. then xy
The adder 13 performs addition processing on the output values obtained based on the Y value and the designated lookup table, and outputs addresses X and Y for reading from the image memory 21.

Based on the X and Y values, when the horizontal clock signal is at a low level, the corresponding image data is read out from the image memory 21 and displayed at the scan position at that time. Then, the next time the horizontal clock signal becomes low level, image data is read out and displayed based on the newly determined X and Y values. This is repeated thereafter.

When the horizontal clock signal is at a high level, the one-company switching circuit 19 replaces the sequential address signal from the sequential address generation circuit 17 with the address signal from the address generation device 1 and inputs it to the image memory 21 as a write address signal. do. As a result, the image memory 21 sequentially reads the latest imaging data from the television camera 23.

Also, the lookup table memory 9 by the CPU 14
When table data is written to the unread side of a and 9b, the address switching selector section 7
And the data switching selector section 11 is switched. This allows the lookup table memory 9a to be read.

9b is replaced, the table with new contents is referred to, and a new display is made.

As described above, in this embodiment, the contents of the lookup table memories 9a and 9b can be easily switched as desired, so various types of free expression on the CRT 29 can be made without adding or changing circuits. becomes. Furthermore, since a multiplication circuit is not used for address calculation, the processing is extremely quick and takes a constant amount of time. Further, two lookup table memories 9a and 9b are provided, and the lookup table memory 9a is controlled by the functions of the address switching selector section 7 and the data switching selector section 11.

Since there is no conflict between read access and write access to 9b, a stable and high quality image can always be obtained. Of course, as long as there is no problem with screen disturbance during rewriting, the lookup table section 9 may have only one lookup table memory, and reading and writing may be performed in the same table memory.
Just execute the import.

In the above embodiment, the window generation circuit 5 (5-2) has two window tables 5a-1 and 5b-1 (5a-2).
, 5b-2) (although not rewritten, its X window table 5 a-1 (5a-2) and
Two window tables 5b-1 (5b-2) may also be provided and made rewritable by the CPU 14. Of course, as long as screen disturbance is not a problem (one X window table 5a-1 (5a-2) and one y window table 5b-1 (5b-2) may be used).

The present invention is configured to convert parameters using a table, and the table itself can be rewritten according to a desired display state. Therefore, despite the simple configuration, display with a high degree of freedom is possible. Furthermore, the image can be read out from the image memory in a short period of time, allowing stable display.

[Brief explanation of the drawing]

Fig. 1 is a basic configuration diagram conceptually illustrating the contents of the present invention, Fig. 2 is a block diagram showing an embodiment of the address generation device for digital image display of the present invention, and Fig. 3 is a diagram showing the address generation device. 4(a) to 4(d) are block diagrams of the lookup table memory, FIG. 5 is a block diagram of the first example of the window generation circuit, and FIG. 6 is a block diagram of the digital image display device used.
The figure is an explanatory diagram of the display state for the window table, FIG. 7 is a configuration diagram of a second example of the window generation circuit, and FIG.
The figure shows an explanation of the display state for the window table. Figure 9 is a flow chart of the processing executed by the CPU.
FIG. 0 is a circuit diagram of a conventional coordinate conversion circuit. 1...Address generation device 3...Address counter section 5.5-2...Window generation circuit 7...Address switching selector section 9...Lookup table section 9a...First lookup table Memory 9b...
Second lookup table memorized...Data switching selector section 3...Addition section 14...CPU 5...Timing controller 7...Sequential address generation circuit

Claims (1)

[Scope of Claims] An address used in a digital image display device that reads image data at an arbitrary address from image data stored in an image memory and sequentially displays it on a two-dimensional display device, and outputs the address. In the generation device, a parameter generation means for generating a two-dimensional parameter indicating a display position of the two-dimensional display device, based on a first parameter among the two-dimensional parameters,
a first conversion means that outputs a first conversion value with reference to a first table; and based on a second parameter among the two-dimensional parameters,
a second conversion means that outputs a second conversion value with reference to a second table; and at least one unit that adds or subtracts the first conversion value and the second conversion value to determine a read address for the image memory. 1. An address generation device for digital image display, comprising: addition/subtraction means for calculating parameters; and table changing means for rewriting the first table and the second table according to a desired display state.