JPH03144843A - Data processor - Google Patents

Abstract

PURPOSE:To attain the use of a FIFO memory of small capacity by reading data directly and simultaneously out of plural FIFO memories after the data equivalent to one word are written on a data bus. CONSTITUTION:The FIFO memories 1 - 4 are provided in number equal to the number obtained by dividing the number of bits of a data bus 6 having a large number of bits by the number of bits of a data bus 5 having a small number of bits. At transfer of the data, the frequency of the data write signal is counted and the FIFO memories to which the data are written are successively selected based on the count value. Then the data are simultaneously and directly read out of the memories 1 - 4 after the data equivalent to one byte of a data bus 6 having a large number of bits are written. Thus the hardware quantity can be reduced and at the same time the hardware can be simplified. Furthermore a FIFO memory having small capacity can be used at a low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a data processing device, and more particularly to data transfer from a data bus with a small number of bits to a data bus with a large number of bits.

(Prior art) Conventionally, when data is transferred from a data bus with a small number of bits to a data bus with a larger number of bits, an F of the same number of bits as this data bus is used.
IF (, lAccumulate data in memory once, then use FIFO
A number of data read-only registers corresponding to the number of bits of the data bus with a large number of bits are provided on the output side of the memory.
The number of bits of the data bus has been converted by reading the contents of the register.

(Problem to be Solved by the Invention) The data transfer method from the conventional data bus with a small number of bits to a data bus with a large number of bits is FIF.
Control hardware is required for the interface between the O memory and the register for reading data. Therefore,
The harder the number of bits of the data bus on the output side becomes, the more
There is a drawback that the amount of hardware on the output side of the FO memory increases and becomes complicated.

Furthermore, since buffering is performed using one FIFO memory, there is a drawback that a large-capacity FIFO memory is required.

An object of the present invention is to provide FIFO memories 'fI' whose number is equal to the number of bits of a data bus with a large number of bits divided by the number of bits of a data bus with a small number of bits.

During data transfer, the number of data write signals is counted, and the FIFO memory to which data is to be written is selected in order based on the count value. After 1 byte of data on the data bus with a large number of bits has been written, each FIFO memory is simultaneously The object of the present invention is to provide a data processing device configured to eliminate the above drawbacks by outputting data t-a more directly and to use a small capacity PIF (J memory).

(Means for Solving the Problems) A data processing device according to the present invention includes a plurality of FIF0 memories, a counter, and memory selection means.

This configuration includes a readout control means.

The plurality of FIFO memories are configured to transfer data from the second data bus to the first data bus when the number of bits in the first data bus is an integral multiple of the number of bits in the second data bus. Something.

It has a plurality of numbers equal to an integral multiple of the above.

The counter is for counting the number of data write signals during data transfer.

The memory selection means is an FI that writes data in the order of count.
This is for sequentially selecting one in the FO memo IJ'.

After the read control means finishes writing one word of data on the first data bus.

At the same time, it is used to directly read data from the PIFO memory.

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. In Figure 1, 1 to 4 are RAMs used as FIFO memories, 5 is an 8-bit data bus, 6 is a 32-bit data bus, and 7 is an RA.
M write control counter, 8 is RAM write control decoder, 9 is RAM write address counter, 10 is RAM
M [Output address counter, 11 is the AM% included signal line, and 12 is the RAM read signal line.

13 is a RAM write address bus, 14 is a RAM read address bus, 15 to 18 are areas at the same address in %RAM, 19 is a decoder for determining the end of data transfer, and 20 is a data control register.

RAM1-4 are each dual-port readable/writable storage devices and are used as FIFO memories.

When writing data to RAMs 1 to 4 using the RAM write signal on the 8-bit data bus 5 signal line 11, R
By the counter 7 for AM write control and the decoder 8 for RAM write control.

Write data in the order of RAM1 to RAM4. By RAM write address counter 9! lRAM write address bus 13
The addresses output to are areas 15 to 18 in RAM.
1 is added after data is written to all of them.

Further, when writing data to each RAM 1 to 4, a bit corresponding to each RAM in the data control register 20 is set, and data writing is monitored. After the final data has been written.

The data indicating the completion of the transfer is decoded by the data transfer end determination decoder 19, and the transfer end bit t in the data control register 20 is turned on and the RAM write control counter 7t is reset.

The data output to the 32-bit data bus 6 is RA
The M1-4 output address counter lO simultaneously outputs the data from areas 15-18 of 5RAMs LAM1-4 (indicated by the address output from the output address bus 144c). After the reading from RAMs 1 to 4 is completed, by reading the data control register 20, it is possible to determine whether the data in each RAM is valid or invalid and to determine the final data value. The RAM[output address counter lO is incremented by l after the data control register 20 is read.

By repeating the above operations, data is transferred between the 8-bit data bus and the 32-bit data bus.

Data transfers other than data transfers between 8 bits and 32 bits can also be transferred between data buses that are multiples of integers, using RAM.
This can be easily realized by making 710 changes to the number of items 1 to 4, the count number of the RAM@inclusive control counter 7, and the decoding conditions of the RAM@inclusive control decoder 8.

(Effects of the Invention) As explained above, the present invention includes FIFO memories equal in number to the number of bits of a data bus with a large number of bits divided by the number of bits of a data bus with a small number of bits. Count the number of times and select the FIFO memory in which to write data based on the count value.

After 1 byte of data on a data bus with a large number of bits has been written, the data can be read directly from each FIFO memory at the same time, reducing the amount of hardware and simplifying the Nordware. Furthermore, there is an advantage that a FIFO memory having a smaller capacity and lower cost can be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. 1-4..., RAM 5.6... Data bus 7.
9.10...Counter 8.19...Decoder 11.12...Signal line 1
3.14...Address bus 15-18...Memory area 20...Register

Claims (1)

[Claims] FIFOs whose number is an integral multiple for transferring data from the second data bus to the first data bus when the first data bus has an integral multiple of the number of bits of the second data bus. a memory, a counter for counting the number of data write signals when transferring the data, memory selection means for sequentially selecting a FIFO memory to write the data in the order of the count, and the first data bus. 1. A data processing device comprising read control means for reading data directly from said FIFO memory at the same time after writing of said one word of data is completed.