JPH03144996A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a large design alteration even if a PLD and a RAM vary in scale by using the end signal of the control of a control circuit for respective bit line driving circuits constituting a logic block as a control start signal for a trailing-stage control circuit. CONSTITUTION:At the start of writing operation, a clear signal CLR1 is supplied to clear respective FFs 3a, only one data of 1 is supplied to the input terminal D1 of a basic circuit 3 on the side of the terminal bit detecting circuit 2a closest to an L side right after a head bit detected by circuit 2b, and then data of 0 is supplied, so that FFs 3a where 1 is stored move in order every time a clock CK1 is sent. Then a clock CKW is started after the CK1 is sent and only a word line W connected to a circuit 3 for 1 starts; and a write pulse WR1 is inputted to the pulse generator 8 of a shift register 5 on the side of a detecting circuit 4a to start the writing operation, which is repeated in order according to an end signal WO from a circuit 8, thereby finishing the writing of all storage cells.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a VT system in which storage cells are provided between bit lines and word lines arranged in a lattice pattern, for example, P L
D (Programn+able Logic De
vice ) and RAM (Random Access
Regarding the improvement of semiconductor integrated circuits such as memory, it is particularly aimed at eliminating the need for major design changes even if the scale of the semiconductor integrated circuit changes.

[Conventional technology]

In a conventional semiconductor integrated circuit having a configuration in which a memory cell is provided between a bit line and a word line, when data is stored in the memory cell, the word line at the corresponding address is raised and the memory cell is connected between the bit line and the memory cell. At the same time, the bit line is set to a high potential (logical value "1") or a low potential (logical value "0") depending on the data to be stored. In addition, to read data stored in a memory cell, the word line at the corresponding address is activated to establish continuity between the bit line and the word line, and the stored data is recognized according to the potential of the bit line at that time. .

In addition, in such a semiconductor integrated circuit, there is no particular problem because only one word line is activated at a time, but for bit lines, it is better to activate as many lines as possible at the same time to write and read data. Since it has the advantage of requiring short access time, it is possible to
I designed the bit line drive circuit and the control circuit that controls the drive circuit.

[Problem to be solved by the invention]

However, in the above conventional semiconductor integrated circuit,
Since the bit line drive circuit and control circuit are designed individually according to the number of bit lines, if the scale of the integrated circuit differs, it is possible to simply change the scale of the bit line drive circuit and control circuit accordingly. Since it is not possible to do so, it is necessary to redesign the control circuit, etc., which increases design costs and
An unresolved issue was that the design period would inevitably increase.

This invention was made by focusing on such unresolved problems with the conventional technology, and provides a semiconductor integrated circuit that can cope with different scales of PLD'PRAM without making major design changes. It is intended to.

[Means to solve the problem]

To achieve the above object, the present invention provides a semiconductor integrated circuit in which a plurality of bit lines and word lines are arranged in a lattice pattern and memory cells are configured between the bit lines and word lines. A drive circuit control means for controlling a bit line drive circuit that drives the bit lines is provided for each logic block, and these drive circuit control means are connected in series. , and the control end signal '4'B of the previous stage drive circuit control means was used as the control start signal of the next stage drive circuit control means.

[Effect]

Control of the drive circuit control means for each bit line drive circuit constituting the logic block (for example, sending a write pulse)
Since the end signal of is used as the control start signal of the next-stage drive circuit control means connected in series, the plurality of bit lines are sequentially driven for each logic block. Note that the number of bit lines constituting a logical block is appropriately determined in consideration of power consumption.

When changing the scale of an integrated circuit, that is, increasing or decreasing the number of bit lines, the number of bit line drive circuits and drive circuit control means can be increased or decreased by simply increasing or decreasing the number of bit line drive circuits and drive circuit control means. can correspond to

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

1 to 6 are diagrams showing one embodiment of the present invention.

First, to explain the configuration, in FIG. 1, a plurality of bit lines and word lines (not shown in the figure) are arranged in a grid pattern, and between the bit lines and word lines, for example, SRAM (
A memory unit 1 in which memory cells (not shown in the figure) such as static RAM (Static RAM) etc. are formed has a row side program circuit 2 connected to an end of a word line extending in the left-right direction within the memory unit 1; Data is written and read by a column-side program circuit 4 connected to bit lines extending in the vertical direction.

The row side program circuit 2 has a second
A row-side shift register 2C is provided in which row-side basic circuits 3 as shown in the figure are connected in series in the number of word lines.

Each row side basic circuit 3 has a two-phase clock CK.

CK! and a flip-flop 3a to which a clear signal CLR is supplied, and an output terminal Q of this flip-flop 3a is connected to an input terminal D1 of the next-stage low-side basic circuit 30, and an inverter 3b and a NOR It is connected to the word line W via a word line driver 3c consisting of a circuit. In addition, the word line driver 3C has a clock CK that becomes H level only when starting up the word line W.
W is supplied via an inverter 3d.

Therefore, the word line W rises when both the output @Q of the flip-flop 3a and the clock CKW are at H level (logical value "1").

On the other hand, the column side program circuit 4 includes a shift register 5 as shown in FIG. The logic blocks 6 are connected in series as many as the number of logical blocks 6 divided into groups.

Each shift register 5 has a predetermined number of column side basic circuits 7 connected in series as bit line drive circuits to which bit lines B and F are connected, that is, an output terminal Q of the column side basic circuit 7.
, are connected to the input terminal D2 of the column-side basic circuit 7 at the next stage to form a shift register.

Note that among these column-side basic circuits 7, the input terminal D2 of the column-side basic circuit 7 located at the beginning is the last column-side basic circuit configuring another shift register located one position before its own shift register 5. The output terminal Q2 of the column-side basic circuit 7, which is connected to the output terminal of the circuit and is also located at the end, is
It is connected to the input terminal D2 of the first column-side basic circuit constituting the shift register 5 located next to its own shift register 5.

Furthermore, each shift register 5 has a write pulse generator 8 as drive circuit control means, and this write pulse generator 8 is supplied with a write pulse WR.

The write pulse generator 8 is connected in series with the write pulse generators included in other shift registers, and receives a write end signal from the write pulse generator of the other shift register located immediately before its own shift register 5. The receiver takes the write start signal Wl as the write start signal Wl, and one pulse of the write pulses WR immediately after the receiver takes the write start signal Wl as the write pulse WR2.
Immediately after the write pulse WR1 ends, the write end signal W○ is supplied to each column side basic circuit 7 as
It is supplied as a write start signal to the write pulse generator of another shift register located next to its own shift register 5.

The column side basic circuit 7, as shown in FIG. , bit lines B and π, and one output terminal Q of the flip-flop 9 serves as an output terminal Q2 of the column side basic circuit 7.

And for bits 4% B and i, write pulse WR
Bit line drivers 10a and 10b driven by
are present, and precharge circuits 11a and llb, which precharge bits IB and π in response to a precharge signal PC during data reading, are located outside the position where bit line drivers 10a and 10b are present (on the storage unit 1 side). )It is connected to the.

Furthermore, the bit lines B and ■ outside the position where the bit line driver 10 is interposed detect the potential difference between the bit lines B and π, and the data stored in the memory cells of the memory unit 1 is set to the logical value "1". A lead terminal RD is connected to the input side of a sense amplifier 12 that determines whether the signal is "0" or a logical value "0" and controls the sense amplifier 12, and is led out to the outside.

Further, the input terminal D2 of the column side basic circuit 7 is supplied to the NAND circuit 13a, and the input terminal D2 of the column side basic circuit 7 is supplied to the NAND circuit 13a.
is supplied with a write control signal SF that becomes H level when writing data and becomes L level when reading data, and the output of the NAND circuit 13a is the NAND signal SF.
It is supplied to the D circuit 13c.

Furthermore, a read control signal PA which becomes H level when reading data and becomes L level when writing data.
and the output of the sense amplifier 12 are supplied to the NAND circuit 13b, and the output of the NAND circuit 13b is the NAND
It is supplied to the circuit 13c.

The output of the NAND circuit 13c is connected to the input end of the flip-flop 9.

Next, the operation of this embodiment will be explained.

5 and 6 are time charts of each signal in the write sequence of this embodiment.

That is, in order to write data to the entire memory section 1, first,
A clear signal CLRz (see FIG. 5(a)) is supplied to the flip-flops 9 of the column-side basic circuit 7 to clear each flip-flop 9.

After the flip-flop 9 is cleared, the clock CK3 (see FIG. 5) is supplied to each column-side basic circuit 7 of each shift register 5 constituting the column-side program circuit 4.

Then, in this state, since the write control signal SF is at H level and the read control signal PA is at L level, NAND circuit 13. The output of a is determined by the state of the output terminal D2 of the column side basic circuit 7 in the previous stage, and the NAND
Since the output of circuit 13b is always at H level, NAND
The output of the circuit 13c is equal to the state of the output terminal D2 of the column-side basic circuit 7 at the previous stage.

Therefore, since the data in each flip-flop 9 is shifted from the left to the right in FIG. Input terminal D2 of basic circuit 7
If the clock CK is transmitted while sequentially supplying data following the first bit detected by the first bit detection circuit 4b, when the first bit detection circuit 4b detects the first bit, any word line W The data to be stored in the memory cell corresponding to is stored in each flip-flop 9.

Therefore, when the leading bit detection circuit 4b detects the leading bit, it stops the clock CK, and also stops the clock CK.
, (see FIG. 5(C)) to the flip-flops 3a of the row-side basic circuit 3 to shift the data in each flip-flop 3a.

However, to prevent multiple word lines from rising at the same time,
The logical value "1" is stored in only one flip-flop 3a (therefore, all other flip-flops 3a
(the logical value "0" is stored in the memory).

Specifically, at the start of writing, after clearing the data in each flip-flop 3a by supplying the clear signal CLR, the input end of the row-side basic circuit 3 located closest to the row-side terminal bit detection circuit 2a, , the first bit detected by the row side first bit detection circuit 2b is followed by a logical value “
Supply only one data of ``1'', and then supply the logical value ``0''.
'', the flip-flop 3a storing the logical value ``1'' will be sequentially moved every time the clock CK is transmitted.

Then, after the clock CK+ is transmitted, the clock CKW (see FIG. 5(d)) is started.

Then, the output of one inverter 3d of each row-side basic circuit 3 goes to L level, but the output of the other inverter 3b goes to H level,
That is, since the data stored in the flip-flop 3a is at the L level only in the low-side basic circuit 3 where the logic value is "1", the data stored in the flip-flop 3a is the logic value "1" after all. Only the word line W connected to the row-side basic circuit 3 rises.

Then, when the clock CKW rises, a write pulse WR+ (see FIG. 5(e)) is supplied, and the memory unit 1
Writing of data to begins.

First, in the shift register 5 located closest to the terminal bit detection circuit 4a, the write pulse generator 8 receives the rising edge of the clock CKW as a write start signal Wl, and outputs one of the write pulses WR immediately after that as a write start signal Wl. It is supplied to each column-side basic circuit 7 as a pulse WR2.

When the write pulse WR is supplied, the bit line drivers 10a provided on the bit lines B and F in all the column side basic circuits 7 included in the shift register 5.
and 10b are in the driving state, so the flip-flop 9
data Q is supplied to bit line B, and data q is supplied to bit line -.

Therefore, all the bit lines B and - included in the logic block 6 corresponding to the shift register 5 are driven at the same time, so data writing is performed for each logic block 6, and the consumption during writing is reduced. The power is a constant value determined by the bit line B and π included in the logic block 6.

After the write pulse generator 8 finishes transmitting the write pulse WR, it outputs a write end signal W○ to the write pulse generator 8 of the shift register 5 at the next stage.

That is, as shown in FIG. 6, the write pulse generator 8 of the shift register 5 located at an arbitrary position converts the write end signal W○ transmitted by the write pulse generator 8 of the previous shift register 5 into its own write start signal Wl.
One of the light pulses WRI (see figure (a)) immediately after that is set as the light pulse WR (see figure (c)), and each column side base water circuit is When the transmission of the write pulse W R2 is completed, the write end signal WO (see (d) in the same figure) is supplied to the write pulse generator 8 of the next shift register 5, and then the write pulse generator 8 of the next stage 8 receives the previous write end signal WO as the write start signal Wl.

Then, when data is written in the shift register 5 located closest to the leading bit detection circuit 4b,
The shift 1-register 5 write pulse generator 8
In response to the write end signal W○ sent by the clock C
As KW falls (see FIG. 5(d)), a clear signal CLR is transmitted, and the above-described process is repeated.

Therefore, when the above-described write process is performed on all word lines W, writing of data to all memory cells included in the memory section 1 is completed.

In this way, in the above embodiment, data is written in each logical block 6, and the data is written in each logical block 6.
A write pulse generator 8 is provided for each shift register 5 corresponding to , and a special circuit is provided because the write end signal W○ of the previous stage write pulse generator 8 is used as the write start signal Wl of the next stage write pulse generator 8. The power consumption during writing and the format of the data to be written are constant regardless of the size of the storage unit 1, and the column side program circuit can be changed by simply increasing or decreasing the shift register 5 according to the size of the storage unit 1. 4, it is possible to accommodate integrated circuits of various sizes without major design changes.

This has the advantage of reducing design costs and shortening the design period.

In the above embodiment, only the data write sequence to the storage unit 1 has been described, but the present invention can also be applied to, for example, a data read sequence.

That is, if a precharge signal generation circuit is provided for each shift register 5 and the control end signal of the precharge signal generation circuit in the previous stage is used as the control start signal of the precharge signal generation circuit in the next stage, it is possible to Therefore, the power consumption during reading and the format of read data remain constant, and it is possible to support integrated circuits of various sizes without making major design changes.

[Effects of the Invention] As explained above, according to the present invention, it is only necessary to provide a bit line drive circuit and a drive circuit control means according to the number of bit lines constituting an integrated circuit, so a major design change is not required. It is possible to support integrated circuits of various scales without having to do this, which results in lower manufacturing costs and shorter design times, and also because multiple bit lines are driven for each logic block. Various effects can be obtained, such as the power consumption when reading and writing data becomes constant without providing a special circuit and regardless of the scale of the integrated circuit.

[Brief explanation of the drawing]

Fig. 1 is a schematic configuration diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of a basic circuit on the row side, Fig. 3 is a circuit diagram showing an example of a shift register, and Fig. 4 is a basic circuit diagram on the column side. FIG. 5 is a circuit diagram showing an example of the circuit, FIG. 5 is a time chart showing the write sequence, and FIG. 6 is a time chart showing the write sequence in each shift register. DESCRIPTION OF SYMBOLS 1...Storage part, 2...Low side program circuit, 3.
...Row side basic circuit, 4...Column side program circuit, 6...Logic block, 7...Column side basic circuit (
bit line drive circuit), 8... write pulse generator (drive circuit control means), B, U... bit line, W...
...Word line 1 Figure 1 Figure 1

Claims (1)

[Claims] (1) In a semiconductor integrated circuit in which a plurality of bit lines and word lines are arranged in a grid and memory cells are configured between the bit lines and word lines, the bit lines are divided into groups of a predetermined number to form logic blocks. At the same time, a drive circuit control means for controlling a bit line drive circuit that drives the bit line is provided for each logic block, and further, these drive circuit control means are connected in series, and the drive circuit control means of the previous stage is connected in series. A semiconductor integrated circuit characterized in that a control end signal is used as a control start signal for a next stage drive circuit control means.