JPH03145737A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to inhibit a short-channel effect without causing an augmentation in a source resistance regardless of the electrical resistance value of a semiconductor substrate by a method wherein a region, which is located on the lower side of a channel region and opposes to a gate electrode, of a semiconductor base is provided with a void part. CONSTITUTION:Parts, which are exposed through first and second opening parts 33a and 33b of an insulating film 33 on a semiconductor substrate 31, of the substrate 31 are used as seed parts and a semiinsulative GaAs crystal layer 35, for example, is selectively grown on the seed parts as a semiconductor layer. At the time of this growth, as the layer 35 not only is grown on the substrate 31 but also is grown in the direction of a <011> crystal axis, a selective growth of the layer 35 is stopped when a void 47 can be formed, the film thickness of a part, which is located on this void 47, of the layer 35 has a film thickness sufficient for forming a channel region and the position of the void 47 to the channel region becomes a position where the component of a current, which is made to flow through the lower side of the channel region due to a short-channel effect, can efficiently be stopped.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to the structure of a semiconductor element having a channel region and a gate electrode, such as a field effect transistor (hereinafter referred to as FET), and a method for manufacturing the same (related thereto). In particular, the present invention relates to a semiconductor device that can suppress short channel effects, and a method for manufacturing the same.

(Prior Art) FETs are known as one of the important semiconductor elements for configuring electronic devices.

The conventional structure and manufacturing method of such semiconductor devices are described in the literature (PROCEEDINGS OF T).
HEIEEE GALLIUM ARSENIDE I
NTEGRATED CIRCUIT SYMPOSIU
M (proceedinges)
Circuit Symposium) (1983, 10) pp
, 134-137)
S (Metal Sem1 conductor)
This will be explained using an example of FET. Figure 3 (A)-(D)
1 is a diagram used to explain the manufacturing process of this GaAs MESFET, and shows the state of the FET in the main steps in the process using cross-sectional views.

First, ions of n-type impurities such as silicon (293i) are implanted into a predetermined region of a semi-insulating GaAs substrate 11 (hereinafter sometimes referred to as substrate 11) to form a channel region 13. Ru.

Next, the entire surface of the substrate 11 on which the channel region 13 is formed is made of a metal material that can form a Schottky barrier between it and the substrate 11 and has heat resistance, such as a tungsten-aluminum (W/lu) alloy. The gate electrode forming metal layer 15 is formed to have a thickness of, for example, 2,000 to 3,000 layers.

Next, a gate mask layer is formed to have a thickness of about 3,000, for example, on the gate electrode forming region of the gate electrode forming metal layer 15 by lift-off or other suitable method.

Through the steps up to this point, the structure shown in FIG. 3(A) is obtained.

The constituent material of the gate mask layer 17 is a material that hardly generates stress between it and the metal layer 15 for forming the gate electrode, and that can be selectively etched at the interface with the metal layer 15. . Further, the gate mask layer 17 may have a single layer structure or a multilayer structure.

Next, the gate mask layer 17 is used as an etching mask,
The structure shown in FIG. 3(A) is subjected to a dry etching process using, for example, a mixed gas of carbon tetrafluoride and oxygen (CFa102) to form a gate electrode 19 (see FIG. 3(A)). B)).

Note that this etching process is performed using a technique that allows selective etching of only the gate electrode forming metal layer 15. In addition, in this etching process, etching is performed mainly along the direction indicated by the symbol a and a series of broken arrows in FIG. 3(8), or simultaneously. It is also performed in a direction parallel to the main surface of the substrate 11. Therefore, side etching portions 21 are formed at the ends of the gate electrode 19 obtained.

Next, as shown in FIG. 3C, 2981 ions are implanted into the semiconductor substrate 11 using the above-mentioned getmask layer 17 as a mask (indicated by a series of solid arrows in the figure).

), and a source region 23 and a train region 25 are formed, respectively.

Next, only the gate mask layer 17 is removed and the gate electrode 1
9 is exposed to obtain the structure shown in FIG. 3(D).

After that, although not shown in the drawings, a source electrode, a train electrode, and other various components depending on the design are formed on this structure to form a desired semiconductor element (in this case, GaAs).
M E S F E T ) is obtained.

In the conventional semiconductor device disclosed in the above-mentioned document, the source and train regions are formed by ion implantation using the gate mask layer 17 as a mask while the side etching portion 21 is provided on the gate electrode 19. . Therefore, as is clear from FIG. 3(D), the source and train regions 23 and 25, respectively,
The gate electrode 19 is formed with an offset width p1 that is substantially the same as the width of the gate electrode 19 . Therefore, the gate length 1
2, the distance I23 between the source region 23 and the train region 25 is 2β1+ρ2, so by setting the offset width 11 to an appropriately large value, the short channel effect due to the shortening of the gate length β2 can be reduced. Source area 23
This has the advantage that it is possible to suppress the phenomenon in which current flows under the channel region 13, which cannot be controlled by the gate electrode, due to the narrowing of the distance between the gate electrode and the train region 25.

(Problems to be Solved by the Invention) However, in conventional semiconductor devices, in order to suppress the short channel effect caused by shortening the gate length, the gate electrode
Since the offset width of the gate between the source region and the train region must be set large, the source resistance, that is, the electrical resistance between the gate electrode and the source region, increases.
As a result, there was a problem in that the characteristics of the semiconductor element deteriorated.

Furthermore, the short channel effect is caused by the flow of current through the semiconductor substrate portion below the channel region, and therefore is highly dependent on the electrical resistance of the semiconductor substrate. As a result, in the conventional semiconductor device structure, when a semiconductor substrate with low electrical resistance is used, it is difficult to sufficiently suppress the short channel effect.

The present invention has been made in view of the above points, and an object of the present invention is to provide a short channel without increasing the source resistance and regardless of the electrical resistance value of the semiconductor substrate used. It is an object of the present invention to provide a semiconductor element having a structure in which the effects can be suppressed, and a method for manufacturing the same.

(Means for Solving the Problems) In order to achieve this object, according to the first invention of this application, in a semiconductor device having a channel region and a gate electrode on a semiconductor base, It is characterized by having a void in the lower region facing the gate electrode.

Further, according to the method for manufacturing a semiconductor device of the second invention of this application, there is a step of forming an insulating film on a semiconductor substrate, exposing a part of the semiconductor substrate and covering at least a region corresponding to a region where a gate electrode is to be formed. a step of forming a semiconductor layer on the semiconductor substrate by a selective growth method using a portion of the semiconductor substrate exposed from the insulating film as a seed portion; a step of forming a channel region in the semiconductor layer; The method is characterized in that it includes a step of forming a gate electrode on a region of the channel region corresponding to the region where the gate electrode is to be formed.

In carrying out the second invention, it is preferable that the above-mentioned insulating film is provided with openings that expose regions that sandwich the portion of the semiconductor substrate corresponding to the region where the gate electrode is to be formed.

(Function) According to the semiconductor device of the first invention of this application, the current component flowing below the channel region, which is generated by the short channel effect and cannot be controlled by the gate electrode, is blocked by the gap. Therefore, the current component flowing under the channel region can be ignored, so that the gate length can be shortened and the semiconductor substrate can be used regardless of the electrical resistance of the semiconductor substrate.

Further, according to the method for manufacturing a semiconductor device of the second invention of this application, an insulating film is formed which exposes a part of the semiconductor substrate and covers at least a region corresponding to the region where the gate electrode is to be formed, and then the semiconductor device is formed. A semiconductor layer is formed on this semiconductor substrate by a selective growth method using a portion of the substrate exposed from the insulating film as a seed portion. During this selective growth, the semiconductor layer is formed on the insulating film, but the semiconductor layer becomes continuous above the insulating film by lateral growth from the seed portion around the insulating film. As a result, a semiconductor layer is formed on the semiconductor substrate in which a portion corresponding to a region where a gate electrode is to be formed has a void. Since this semiconductor layer and the semiconductor substrate constitute a semiconductor base, a channel region is formed in the upper region of the cavity of the semiconductor layer, and a gate electrode is formed on this channel region (thereby, the semiconductor element of the first invention can be easily obtained). .

It is known that selective growth is performed better when the area of the seed portion is smaller than the area of the portion covered with the insulating film. Therefore, by using an insulating film having openings that expose the regions sandwiching the region of the semiconductor substrate where the gate electrode is to be formed, as in the preferred embodiment of the second invention, selective growth can be carried out efficiently.

(Example) Examples of the semiconductor device and the manufacturing method thereof of this application will be described below with reference to the drawings. It should be noted that the drawings used in the following explanation are only schematic illustrations to the extent that the present invention can be understood. Therefore, it should be understood that the dimensions, shapes, and distribution of each component in the drawings are merely examples, and the present invention is not limited to these. Further, the following embodiments will be explained using an example in which the semiconductor element is a GaAsM ESFET having a Schottky junction gate.

- Announcement 3 days First, the structure of the semiconductor device of the first invention of this application will be explained. FIG. 1 shows an example of GaAsM E 5FET.
FIG. 3 is a schematic cross-sectional view taken parallel to the gate length direction.

In FIG. 1, 31 is a semi-insulating G as a semiconductor substrate.
aAs substrate (hereinafter sometimes abbreviated as semiconductor substrate).

), and 33 indicates an insulating film provided on the semiconductor substrate 31, exposing a part of the semiconductor substrate 31 and covering at least a region corresponding to the region where the gate electrode is to be formed. In addition,
In this embodiment, the insulating film 33 is formed on the semiconductor substrate 31.
A first opening 33a and a second opening 33b that respectively expose a part of the semiconductor substrate 31 are provided on both sides in the gate length direction of the region corresponding to the region where the gate electrode is to be formed.
This is an insulating film with Therefore, the semiconductor substrate 31 in this embodiment has the first and second openings 33a, 33
All areas other than the area exposed by b are covered with an insulating film. Here, the first and second openings 33a.

In this embodiment, the planar shape of 33b is square. However, the first and second openings 33a.

The planar shape of 33b is not limited to this, but may be changed depending on the design. Furthermore, how large the area of the first and second openings 33a and 33b should be, and roughly how large the area of the insulating film between these openings 33a and 33b should be, depends on the size of the gate electrode. It is set to an appropriate value depending on the crystal growth conditions during selective growth, which will be described later.

Generally speaking, in FIG. 1, numeral 35 indicates a semi-insulating GaAs layer. This semi-insulating GaAs layer 35 is connected to the semiconductor substrate 3.
1 constitutes a semiconductor base 37.

A detailed explanation of this semi-insulating GaAs layer 35 will be given in the section on the manufacturing method described later.

Furthermore, in FIG. 1, 39 is a channel region formed in the GaAs layer 35, 41a and 41b are source and train regions, 43a and 43b are source and train electrodes, and 4
Reference numeral 5 indicates gate electrodes provided on the channel region 39, respectively.

Briefly, in FIG. 1, reference numeral 47 indicates a gap provided in a region of the semiconductor base 37 below the channel region 39 and facing the gate electrode 45. This gap 47 is located below the channel region 39, and is provided at a position where it can effectively block the current flowing below the channel region 39, which is caused by the short channel effect and cannot be controlled by the gate electrode 45.

A detailed explanation of this void portion 47 will be given in the section on the manufacturing method described later.

Next to the half-base system, Ga of the embodiment of the first invention explained using FIG.
An embodiment of a method for manufacturing a semiconductor device, which is the second invention of this application, will be explained using an example of manufacturing AsMESFET@. FIGS. 2(A) to 2(F) are process diagrams for explaining the process, and are diagrams showing the state of the element in the main steps in the process using cross-sectional views similar to FIG. 1.

First, as shown in FIG. 2(A), semi-insulating GaAs
An insulating film 3 is formed on the substrate 31 by a suitable method such as CVD.
In this case, the SiC2 film is formed to have a thickness of about 100°λ.

Next, a resist is applied on the insulating film 33, and then a well-known photolithography technique is applied to the resist to form the first opening 51a and the second opening 51a, which are adjacent to each other with a gap of about 2 to 5 um. A first opening 51a and a second opening 51 each having a predetermined area.
b to obtain a resist pattern 51 (see FIG. 2(B)).
)). The first and second openings 51a and 51b of these resist patterns are arranged so that the adjacent direction is the <011> direction with respect to the crystal axis of the semi-insulating GaAs substrate 31.

Next, wet etching using hydrofluoric acid or CF
The insulating film 3 is etched by dry etching using a gas or the like.
3, the portions exposed from the openings 51a and 51b of the resist pattern are selectively removed to form a first opening 33a and a second opening 33b in the insulating film 33 (second opening 33b).
Figure (C)). Here, a portion 33x of the insulating film 33 between the first and second openings 33a and 33b corresponds to an insulating film that covers a region of the semiconductor substrate 31 corresponding to the region where the gate electrode is to be formed.

Next, the resist is removed, and then the semiconductor substrate 31 is
Using the portions of the insulating film 33 exposed from the first and second openings 33a and 33b as seed parts, MOCVD or M
A semi-insulating GaAs crystal layer 35 (hereinafter sometimes abbreviated as GaAs semiconductor layer 35) is selectively grown as a semiconductor layer on the seed portion using a suitable method such as the BE method. During this growth, the GaAs semiconductor layer 35
In addition to growing above the aAs substrate 31,
〉The growth layer also grows in the direction of the crystal axis! <01
When viewed in cross section taken in the 1> direction, it has an inverted mesa shape. Therefore, as the GaAs semiconductor layer 35 starts growing from the seed portions exposed from the first and second openings 33a and 33b, as the growth progresses, the second and second openings 3 of the insulating film 33 grow.
Above the region between 3a and 33b, the layer contacts and becomes a continuous layer.

However, a gap 47 is formed on the insulating film portion between both openings 338.degree. 33b.

The above-described selective growth of the GaAs semiconductor layer 35 allows the formation of the void 47 and the thickness of the portion of the GaAs layer 35 above the void 47 that is sufficient to form a channel region, and the position of the void 47 relative to the channel region. When the current component flowing under the channel region due to the short channel effect can be effectively roughened, the process is stopped (FIG. 2(D)).

Next, for example, Si ions are implanted into the GaAs semiconductor layer 35 obtained by selective growth to form a channel region 39 (FIG. 2(E)).

Next, the channel region 39 is made of a heat-resistant Schottky metal, for example, W-AQ, so as to be located on a region corresponding to the central portion of the portion 33x between the first and second openings 33a and 33b of the insulating film 33. The gate electrode 45 is formed by a known method (FIG. 2(F)).

Next, this gate electrode 45 is used as a mask and made of GaAs.
Si ions are implanted into the semiconductor layer 35 by self-alignment to form source and train regions 41a and 41b. Subsequently, after activating the implanted Si ions by heat treatment, a source electrode and a train electrode 43 as ohmic electrodes are formed in the source and train regions 41a and 41b.
a, 43b @ formed respectively, and GaAs shown in FIG.
Obtain M E S F E T .

Note that the end portion of the semiconductor layer 35 grown by the selective growth method has an eave shape and forms a step between it and the semiconductor substrate 31.

If this level difference poses a problem in device formation, it can be dealt with by a known planarization process or the like.

The above is the description of each embodiment of the semiconductor device and its manufacturing method of this application. However, these inventions are not limited to the above-described embodiments, and can be modified in various ways as described below.

The embodiment of the semiconductor device described above uses the structure of the first invention as GaA.
This was an example applied to sMESFET. However, the structure of the first invention is suitable for use with other semiconductor devices, such as HE
It is clear that the present invention can also be applied to MTs, MOS type FETs whose gates are made of metal/insulating film/semiconductor, FETs having an LDD structure, and the like.

Further, in the embodiment of the method for manufacturing a semiconductor device described above, the first and second openings 33a are formed on the semiconductor substrate 31.

33b is formed and these openings 33a are formed.
.

This was an example in which selective growth was performed using the semiconductor substrate portion exposed from 33b as a seed part. However, the insulating film is
It is considered that the purpose can be achieved even if the gate electrode is provided in a region corresponding to the region where the gate electrode is to be formed.

Further, in the above-described embodiment of the manufacturing method, the insulating film 33 was composed of a SiO2 film having a thickness of 1000 mm. However, the thickness and constituent materials of the insulating film are not limited to these, and can be changed depending on the design.

Further, in the embodiment of the manufacturing method described above, the gate electrode 45 is used as a mask to perform ion implantation to form the source and train regions using the self-alignment line. but,
Of course, a step such as providing an offset region between the gate electrode and the source and train regions may be added.

Further, in each of the embodiments of the first and second inventions described above, the semiconductor element was a GaAs-based semiconductor element. However, these inventions are also applicable to cases in which the semiconductor element is made of other materials, such as other ■-V group compound semiconductor materials, silicon, or the like.

(Effects of the Invention) As is clear from the above description, according to the semiconductor device of the first invention of this application, in a semiconductor device including a channel region and a gate electrode on a semiconductor base, the channel region of the semiconductor base is Since there is a void in the lower region facing the gate electrode, the current component flowing to the bottom of the channel region, which is caused by the short channel effect and cannot be controlled by the gate electrode, is blocked by this void. . Therefore, even in a device with a short gate length, the short channel effect can be suppressed while reducing the source resistance, thereby improving the characteristics of the semiconductor element.

Furthermore, since it becomes possible to use a large substrate with a low electrical resistance and a large τ1, the degree of freedom in design is improved.

Further, according to the method for manufacturing a semiconductor device of the second invention of this application, there is provided a semiconductor device comprising a channel region and a gate electrode on a semiconductor base, wherein the semiconductor base has a region below the channel region and a gate electrode. Since it is possible to easily manufacture a semiconductor element with a void in the opposing regions, the short channel effect can be achieved without increasing the source resistance, and regardless of the electrical resistance value of the semiconductor substrate used. Therefore, it is possible to easily provide a semiconductor element having a structure that can suppress this.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an example, FIGS. 2(A) to (F) are process diagrams for explaining an example of a manufacturing method, and FIGS. ) is an explanatory diagram of the prior art. 31... Semiconductor substrate, 33... Insulating film 33a
...First opening 33b of the insulating film...Second opening 35 of the insulating film...Semiconductor layer 39 by selective growth method...Channel region Drainage region Train electrode 47...Void portion 37... ...Semiconductor base, 41a, 41b--Source, 43a, 43b--Source, 45...Gate electrode, 51...Resist, ゛＼tan 51a...First opening 51b of resist pattern...
- Second opening 33× of resist baton: a portion located between the openings of the insulating film.

Claims (3)

[Claims] (1) A semiconductor device comprising a channel region and a gate electrode on a semiconductor base, characterized in that the semiconductor base has a void in a region below the channel region and facing the gate electrode. . (2) forming an insulating film on a semiconductor substrate that exposes a part of the semiconductor substrate and covers at least a region corresponding to a region where a gate electrode is to be formed; A step of forming a semiconductor layer as a seed portion on the semiconductor substrate by a selective growth method, a step of forming a channel region in the semiconductor layer, and a step of forming a gate electrode on a region of the channel region corresponding to the region where the gate electrode is to be formed. 1. A method for manufacturing a semiconductor device, the method comprising: forming a semiconductor device. (3) The method for manufacturing a semiconductor device according to claim 2, wherein the insulating film has openings that expose regions sandwiching a portion of the semiconductor substrate corresponding to a region where a gate electrode is to be formed. Features and manufacturing methods of semiconductor devices.