JPH0314805U - - Google Patents
Info
- Publication number
- JPH0314805U JPH0314805U JP1989074474U JP7447489U JPH0314805U JP H0314805 U JPH0314805 U JP H0314805U JP 1989074474 U JP1989074474 U JP 1989074474U JP 7447489 U JP7447489 U JP 7447489U JP H0314805 U JPH0314805 U JP H0314805U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- carrier
- monolithic integrated
- view
- perspective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
Landscapes
- Mounting Of Printed Circuit Boards And The Like (AREA)
- Die Bonding (AREA)
- Waveguides (AREA)
Description
第１図はこの考案の一実施例によるモノリシツ
ク集積回路用キヤリアを示す斜視図、第２図はこ
の考案のキヤリアにモノリシツク集積回路を装着
した時の側面図、第３図はこの考案の他の実施例
を示すモノリシツク集積回路用キヤリアを示す斜
視図、第４図は一般に用いられているモノリシツ
ク集積回路の斜視図、第５図はモノリシツク集積
回路をキヤリアに装着する場合の一例を示す斜視
図、第６図は従来のモノリシツク集積回路用キヤ
リアを示す斜視図、第７図は従来のキヤリアにモ
ノリシツク集積回路を装着した時の側面図である
。
図中、１……半導体基板、４……金属、５……
キヤリア、６……マイクロ波集積回路、７……金
属細線、８……半田、９……凹部である。なお、
図中、同一符号は同一、又は相当部分を示す。
Fig. 1 is a perspective view showing a carrier for a monolithic integrated circuit according to one embodiment of this invention, Fig. 2 is a side view when a monolithic integrated circuit is mounted on the carrier of this invention, and Fig. 3 is another embodiment of this invention. FIG. 4 is a perspective view of a commonly used monolithic integrated circuit carrier; FIG. 5 is a perspective view of an example of mounting a monolithic integrated circuit on a carrier; FIG. 6 is a perspective view showing a conventional carrier for a monolithic integrated circuit, and FIG. 7 is a side view of the conventional carrier with a monolithic integrated circuit mounted thereon. In the figure, 1... semiconductor substrate, 4... metal, 5...
Carrier, 6...Microwave integrated circuit, 7...Metal thin wire, 8...Solder, 9...Concave portion. In addition,
In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
とを一体形成し、上記半導体基板の裏面には比較
的厚い金属を設けて成るＰＨＳ（ＰｌａｔｅｄＨ
ｅａｔＳｉｎｋ）構造のモノリシツク集積回路を
装着するキヤリアにおいて、上記キヤリアのほぼ
中央部になめらかな曲線状の凹部を設けた事を特
徴とするモノリシツク集積回路用キヤリア。 PHS (Plated H
1. A carrier for a monolithic integrated circuit on which a monolithic integrated circuit having an eatSink structure is mounted, characterized in that a smooth curved recess is provided approximately in the center of the carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989074474U JPH0314805U (en) | 1989-06-26 | 1989-06-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989074474U JPH0314805U (en) | 1989-06-26 | 1989-06-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0314805U true JPH0314805U (en) | 1991-02-14 |
Family
ID=31614192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989074474U Pending JPH0314805U (en) | 1989-06-26 | 1989-06-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0314805U (en) |
-
1989
- 1989-06-26 JP JP1989074474U patent/JPH0314805U/ja active Pending