JPH03153045A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03153045A
JPH03153045A JP29262189A JP29262189A JPH03153045A JP H03153045 A JPH03153045 A JP H03153045A JP 29262189 A JP29262189 A JP 29262189A JP 29262189 A JP29262189 A JP 29262189A JP H03153045 A JPH03153045 A JP H03153045A
Authority
JP
Japan
Prior art keywords
gate electrode
oxide film
silicon oxide
sidewalls
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29262189A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamamoto
宏 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP29262189A priority Critical patent/JPH03153045A/en
Publication of JPH03153045A publication Critical patent/JPH03153045A/en
Pending legal-status Critical Current

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To eliminate an irregularity in sidewalls of a gate electrode and to realize a uniform transistor characteristic over a wafer by a method wherein an ozone- and organic silicon-based silicon oxide film is used to form the sidewalls of the gate electrode. CONSTITUTION:A well 12 and a LOCOS 13 are formed on a semiconductor substrate 11; after that, a gate insulating film 14 is formed in a high-temperature oxidizing atmosphere; in succession, polycrystalline silicon is vapor-grown. Then, a patterning operation is executed by a dry etching operation by making use of the polycrystalline silicon as a mask; a gate electrode 15 is formed. In succession, low-concentration ions are implanted by making use of a photoresist as a mask. In order to form a silicon oxide film for sidewalls, organic silane and oxygen gas containing ozone are introduced into a reaction container and are vapor-grown by a bubbling operation using an inert gas as a carrier gas. After that, an anisotropic dry etching operation is executed by using an etching gas; the silicon oxide film is left selectively on side faces of the gate electrode.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の特にMO5I−ランジスタの製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing semiconductor devices, particularly MO5I transistors.

〔従来の技術] 従来、微細化された半導体装置の製造方法は、L D 
D (Lightly Doped Drain )構
造のMOSトランジスタを例にとると、第2図に示すよ
うにWel122、LOCO323を形成した半導体基
板21にゲート絶縁Il!24を高温酸化雰囲気中で形
成した後、多結晶シリコン膜を約0.4μm気相成長さ
せ、これをフォトレジストをマスクしてドライエツチン
グによってパターニングを行い、ゲート電極25を形成
する。続いてフォトレジストをマスクとして低濃度の不
純物を打ち込んだ後、基板全面にモノシランを原料とし
た気相成長による酸化シリコン膜を約0.5μm堆積し
、基板に垂直に異方性ドライエツチングを行なうことに
よってゲート電極の側面に選択的に酸化シリコン膜を残
して、サイドウオール26を形成している。その後高濃
度のイオンを打ち込むことによってソース・ドレイン領
域を形成し、第2フイールド絶縁膜27を気相成長によ
って形成した後、コンタクトホールをフォトレジストを
マスクとして開孔し、アルミニニウム合金を0.5〜1
.0μmスパッタする0次に、フォトレジストをマスク
として、ドライエツチングによってバターニングし配線
としている。
[Prior Art] Conventionally, a method for manufacturing a miniaturized semiconductor device is L D
Taking a D (Lightly Doped Drain) structure MOS transistor as an example, as shown in FIG. 2, a gate insulator Il! After forming 24 in a high-temperature oxidizing atmosphere, a polycrystalline silicon film is grown in a vapor phase to a thickness of about 0.4 μm, and this is patterned by dry etching using a photoresist mask to form a gate electrode 25. Next, after implanting low concentration impurities using a photoresist as a mask, a silicon oxide film of about 0.5 μm is deposited on the entire surface of the substrate by vapor phase growth using monosilane as a raw material, and anisotropic dry etching is performed perpendicular to the substrate. As a result, the silicon oxide film is selectively left on the side surfaces of the gate electrode to form sidewalls 26. Thereafter, source/drain regions are formed by implanting high-concentration ions, and a second field insulating film 27 is formed by vapor phase growth. Contact holes are then opened using a photoresist as a mask, and aluminum alloy is deposited in a 0.0-. 5-1
.. After 0 μm sputtering, patterning is performed by dry etching using a photoresist as a mask to form wiring.

[発明が解決しようとする課題1 しかしながら、従来技術では、第3図に示すように、モ
ノシランを原料としたCVD酸化シリコン膜36の側壁
部の付き回りが段差上部の60%程度であるため、サイ
ドウオール形成に必要な酸化シリコン膜を厚くしなけれ
がならない、ゲート電極上やアクティブ領域上の酸化シ
リコン膜が厚くなるとエッチパックする時間が長くなり
、ウェハー内のエツチングレートの差によってサイドウ
オールの幅のばらつきを大きくする原因となる。
[Problem to be Solved by the Invention 1] However, in the prior art, as shown in FIG. 3, the coverage of the side wall portion of the CVD silicon oxide film 36 made from monosilane is about 60% of the top of the step. The silicon oxide film required for sidewall formation must be made thicker. The thicker the silicon oxide film on the gate electrode or active region, the longer the etch-packing time will be. This causes a large variation in the results.

LDD構造におけるサイドウオールはトランジスタの特
性に与える影響が大きく、例^ばサイドウオールの幅が
狭すぎるとホットエレクトロンに対して弱(なる。
The sidewalls in an LDD structure have a large effect on the characteristics of the transistor; for example, if the width of the sidewalls is too narrow, it becomes vulnerable to hot electrons.

また、CVD酸化シリコン膜の付き回りがウェハー内で
ばらつくために部分的にオーバーエッチとなりゲート電
極とサイドウオールに段差が生じ、続く第2フイールド
のCVD酸化シリコン膜の堆積でもなくならず、ゲート
itiの上を横切るアルミニュウム配線の断線の原因と
なる。
In addition, because the coverage of the CVD silicon oxide film varies within the wafer, it is partially overetched, creating a step between the gate electrode and the sidewall, which does not disappear even with the subsequent deposition of the CVD silicon oxide film in the second field. This may cause the aluminum wiring that crosses over the wire to break.

しかるに、本発明は、かかる課題を解決するものであり
、その目的とするところはゲート電極側壁のサイドウオ
ールのばらつきを無くし、ウェハー内で均一なトランジ
スタ特性を実現し、歩留りが高く、信頼性の高い半導体
装置を供給することにある。
However, the present invention is intended to solve such problems, and its purpose is to eliminate variations in the sidewalls of the gate electrode sidewalls, realize uniform transistor characteristics within the wafer, and achieve high yield and reliability. Our goal is to provide high quality semiconductor devices.

[課題を解決するための手段1 本発明の半導体装置の製造方法は、MOSトランジスタ
のゲート電極の側壁にサイドウオールを有する半導体装
置において、上記サイドウオールが、有機シランとオゾ
ンを含む酸素雰囲気中で反応させた酸化シリコン膜で形
成されていることを特徴とする。
[Means for Solving the Problems 1] The method for manufacturing a semiconductor device of the present invention provides a semiconductor device having a sidewall on the side wall of a gate electrode of a MOS transistor, in which the sidewall is placed in an oxygen atmosphere containing organic silane and ozone. It is characterized by being formed from a reacted silicon oxide film.

[実 施 例1 以下本発明の実施例における工程を、第1図に基づいて
詳細に説明する。
[Example 1] Hereinafter, steps in an example of the present invention will be explained in detail based on FIG. 1.

まず8図のごとく、半導体基板11上にWELL12.
LOCO513を形成した後、ゲート絶縁11114を
高温酸化雰囲気中で形成し、続いて多結晶シリコンを約
0.4μm気相成長させる0次にb図のごとく、上記多
結晶シリコンをフォトレジストをマスクとしてドライエ
ツチングによってバターニングを行い、ゲート電極15
を形成する。続いてフォトレジストをマスクとして低濃
度のイオンを打ち込む、サイドウオール16の酸化シリ
コン膜の形成は、HeやN8等の不活性ガスをキャリア
ガスとしたバブリングによってTEOS([Si  (
QC28s)4])等の有機シランと、オゾンを約5%
含む酸素ガスを、約100Torr、基板温度的350
℃に保った反応器内に導入し約0.4μm気相成長させ
ている。その後、CF410オ等のエツチングガスによ
って異方性ドライエツチングを行なうことによってゲー
ト電極の側面に選択的に酸化シリコン膜を残す。
First, as shown in FIG. 8, a WELL 12.
After forming the LOCO 513, a gate insulator 11114 is formed in a high-temperature oxidizing atmosphere, and then polycrystalline silicon is grown in a vapor phase to a thickness of about 0.4 μm. Buttering is performed by dry etching to form the gate electrode 15.
form. Next, low-concentration ions are implanted using the photoresist as a mask to form the silicon oxide film of the sidewall 16. TEOS ([Si (
Organic silane such as QC28s)4]) and ozone at about 5%
Containing oxygen gas at approximately 100 Torr and substrate temperature at 350 Torr.
It was introduced into a reactor kept at ℃ and grown to about 0.4 μm in vapor phase. Thereafter, by performing anisotropic dry etching using an etching gas such as CF410, a silicon oxide film is selectively left on the side surfaces of the gate electrode.

続いて、高1度のイオン打ち込みによってソース・ドレ
イン領域を形成する。この後、C図のごとく第2フイー
ルド絶縁膜17を気相成長によって形成した後、コンタ
クトホールをフォトレジストをマスクとして開孔し、ア
ルミニュウム合金な05〜1.0μmスパックする0次
に、フォトレジストをマスクとして、C12やBcts
のようなハロゲン系ガスによってドライエツチングして
バターニングし配!Ji18とする。
Subsequently, source/drain regions are formed by high-degree ion implantation. After that, as shown in Fig. C, a second field insulating film 17 is formed by vapor phase growth, and a contact hole is opened using a photoresist as a mask. As a mask, C12 and Bcts
Dry etched and buttered with halogen gas such as Let's say Ji18.

この様にしてなる半導体装置は、オゾン−有機シリコン
系の酸化シリコン膜の段差側面部の付き回りが100%
に近く、モノシラン系の酸化シリコン膜に比べて、サイ
ドウオールをつくるに必要な膜厚を20〜50%薄くす
ることができ、この酸化シリコン膜をエツチングする時
間が短縮できるとともにウェハー内のサイドウオールの
幅のばらつきを小さくすることが可能である。
In the semiconductor device made in this way, the coverage of the ozone-organosilicon based silicon oxide film on the stepped side surface is 100%.
Compared to monosilane-based silicon oxide films, the film thickness required to form sidewalls can be reduced by 20 to 50%, and the time to etch this silicon oxide film can be shortened. It is possible to reduce the variation in the width of the .

〔発明の効果1 以上のごと(、本発明によれば、ゲート電極のサイドウ
オール形成にオゾン−有機シリコン系酸化シリコン膜を
用いることによって、トランジスタ特性のばらつきを小
さくする事ができ、歩留まりが高くかつ信頼性の高い半
導体装置を提供することが出来る。
[Effect of the invention 1 As described above] According to the present invention, by using an ozone-organosilicon-based silicon oxide film to form the sidewall of the gate electrode, variations in transistor characteristics can be reduced and the yield is high. Moreover, a highly reliable semiconductor device can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(c)は、本発明の半導体装置の製造方
法の一実施例を示す断面図である。 第2図は、従来の半導体製造方法を示す断面図である。 第3図は、シラン系の酸化シリコン膜の段差被覆性を示
す断面図である。 11 、2 l 、 3 l ・ l 2、22、32 13、23、33 ・ 14、24、34 ・ l 5、25、35 ・ l 6、26 ・ ・ ・ ・ 17、27 ・ ・ ・ ・ 18、28 ・ ・ ・ ・ l 9、29 ・ ・ ・ ・ l Ol 20 ・ ・ ・ ・ 36 ・ ・ ・ ・ ・ ・ ・ 半導体基板 ・Well ・LOGOS ゲート酸化膜 ・ゲート電極 ・サイドウオール ・第2フイールド ・アルミニュウム配線 ・低濃度イオン注入領域 ・高濃度イオン注入領域 ・シラン系CVDflit化シリ コン膜
FIGS. 1(a) to 1(c) are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 2 is a cross-sectional view showing a conventional semiconductor manufacturing method. FIG. 3 is a cross-sectional view showing the step coverage of a silane-based silicon oxide film. 11, 2 l, 3 l ・ l 2, 22, 32 13, 23, 33 ・ 14, 24, 34 ・ l 5, 25, 35 ・ l 6, 26 ・ ・ ・ ・ 17, 27 ・ ・ ・ ・ 18, 28 ・ ・ ・ ・ ・ l 9, 29 ・ ・ ・ ・ ・ l Ol 20 ・ ・ ・ ・ 36 ・ ・ ・ ・ ・ ・ ・ Semiconductor substrate/Well ・LOGOS Gate oxide film/Gate electrode/Side wall/Second field/Aluminum wiring・Low concentration ion implantation region ・High concentration ion implantation region ・Silane-based CVD flit silicon film

Claims (1)

【特許請求の範囲】[Claims]  MOSトランジスタのゲート電極の側壁に絶縁膜から
なるスペーサー(以下サイドウォールという)を有する
半導体装置において、上記サイドウォールが、有機シラ
ンとオゾンを含む酸素雰囲気中で、反応させた酸化シリ
コン膜で形成されていることを特徴とする半導体装置の
製造方法。
In a semiconductor device having a spacer (hereinafter referred to as a sidewall) made of an insulating film on the sidewall of a gate electrode of a MOS transistor, the sidewall is formed of a silicon oxide film reacted in an oxygen atmosphere containing organic silane and ozone. A method of manufacturing a semiconductor device, characterized in that:
JP29262189A 1989-11-10 1989-11-10 Manufacture of semiconductor device Pending JPH03153045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29262189A JPH03153045A (en) 1989-11-10 1989-11-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29262189A JPH03153045A (en) 1989-11-10 1989-11-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03153045A true JPH03153045A (en) 1991-07-01

Family

ID=17784170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29262189A Pending JPH03153045A (en) 1989-11-10 1989-11-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03153045A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1284015A4 (en) * 2000-04-28 2005-07-20 Tokyo Electron Ltd SEMICONDUCTOR COMPONENT WITH A LOW DIELECTRICITY FILM AND METHOD OF MANUFACTURING THEREOF

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1284015A4 (en) * 2000-04-28 2005-07-20 Tokyo Electron Ltd SEMICONDUCTOR COMPONENT WITH A LOW DIELECTRICITY FILM AND METHOD OF MANUFACTURING THEREOF

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