JPH03154347A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce junction capacitance between a collector and a substrate and between a base and the collector and then, contrive to speed up a bipolar transistor by covering side walls of a increased part with a 3rd insulating film prior to the formation of a channel stopper layer. CONSTITUTION:An oxide film is formed extensively as a 3rd insulating film 6 by a CVD process and then, the above insulating film 6 is left only at side wall parts of a recessed place by anisotropic dry etching and another part of the film 6 is etched. Subsequently, ion implantation is performed extensively according to a system like self-alignment. ln such a case, the 3rd insulating film 6 at the side walls of the recessed place acts as an injection-stopping film and a channel stopper layer 7 is formed only at the base of the recessed place. Then, after removing a 1st insulating film 4 and a 2nd insulating film 5, boron ions are injected and diffused and then, a P-type base layer 9 is formed. As a result, the lateral diffusion of the channel stopper layer 7 is prevented and further, contact is not made among the channel stopper layer 7 and a buried layer 2 and the base layer 9. In this way, junction capacitance between a collector and a substrate and between the base and the collector is reduced and thus high-speed operation is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device with improved high frequency characteristics of a bipolar transistor.

2. Description of the Related Art In semiconductor devices in which bipolar transistors are integrated, an insulating film separation method is applied in order to reduce junction capacitance and achieve higher speeds.

In this method, it is essential to form a channel stopper layer in order to electrically insulate and separate adjacent buried layers of the second conductivity type.

Conventionally, the formation of this channel stopper layer was performed as shown in FIG.
), (b), and (c) are shown in the step-by-step cross-sectional views. This method starts with Figure 2 (
As shown in a), an N-type buried layer 2 on a P-type semiconductor substrate l
The epitaxial layer N3, which will become the isolation region adjacent to the first
After selectively etching the thermal oxide film as the insulating film 4 and the nitride film as the second insulating film 5 as a mask to form a recess, a channel stopper layer 7 is formed by ion implantation.

Thereafter, as shown in FIG. 2(b), the channel stopper M7 is deeply diffused so as to overlap the P-type semiconductor substrate 1 by a thermal diffusion method. Thereafter, as shown in FIG. 2(c), an isolation oxide film is formed as the fourth insulating film 8, and a P-type base N9 is formed in the epitaxial layer 3 on the N-type buried N2. At this time, the channel stopper N7 was in contact with the N-type buried layer N2, and at the same time, the channel stopper lateral diffusion layer 10 was also in contact with the N-type buried layer 2.

Problems to be Solved by the Invention However, in the conventional manufacturing method described above, when ion implantation is performed to form the channel stopper layer 7, the epitaxial layer 3 on the side wall of the recess that will become the isolation region is exposed to the recess. Therefore, the channel stopper layer 7 also spreads in the lateral direction during diffusion. For this reason, the channel stopper layer 7 and the N-type buried N2 end up in direct contact, and the collector-substrate junction capacitance of the bipolar transistor increases. Further, the P type base layer 9 and the N type buried N2 are connected through the channel stopper lateral diffusion layer 10,
This has serious disadvantages in that the capacitance between the base and collector increases and the high frequency characteristics of the transistor deteriorate.

The present invention solves the above-mentioned conventional problems by preventing contact between a channel stopper layer and an N-type buried layer, preventing an increase in collector-substrate junction capacitance and base-collector junction capacitance of a transistor, An object of the present invention is to provide a method for manufacturing a semiconductor device that enables high-speed operation.

Means for Solving the Problems In the method for manufacturing a semiconductor device of the present invention, before forming a channel stopper layer, an insulating film is formed only on the sidewalls of a recess that will become an isolation region, and the epitaxial layer on the sidewalls is It is covered with an insulating film.

Operation According to the method of the present invention, ion implantation for forming a channel stopper is performed in a self-aligned manner, and the channel stopper layer is formed by an insulating film formed on the side wall of the recess as an injection blocking film during ion implantation. It is not formed directly under the insulating film on the side wall portion of the side wall portion, but is formed only on the bottom portion of the recess. Therefore, lateral diffusion of the channel stopper layer can be prevented, there is no contact between the channel stopper layer and the buried layer and the base layer, reducing collector-substrate and base-collector leap junction capacitance, and improving the high frequency characteristics of bipolar transistors. It can be achieved.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIGS. 1A to 1H are cross-sectional views in the order of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1(a), an N-type buried layer 2 is selectively formed in a portion of a semiconductor substrate 1, such as a P-type silicon single crystal, which will become an element region. This method is performed by, for example, antimony ion implantation. Thereafter, an epitaxial layer 3 of about 1 μm is formed thereon. Then the first
A thermal oxide film with a thickness of about 50 nm is used as the insulating film 4, and a second insulating film 5
A nitride film of about 1100 nm is formed as a nitride film, and an opening S is selectively formed only in a portion that will become an isolation region.

Thereafter, as shown in FIG. 1(b), using the first insulating film 4 and the second insulating film 5 as masks, the epitaxial layer rM3 in the opening S is etched by an anisotropic dry etching method using a chlorine-based gas. Then, it is etched by about 500 nm.

Next, as shown in FIG. 1(c), an oxide film having a thickness of about 1 μm is formed over the entire surface as the third insulating layer III 6 by, for example, the CVD method.

Next, as shown in FIG. 1(d), by anisotropic dry etching, the third insulating film 6 is left only on the side walls of the recess.
Others are eroded.

Next, as shown in FIG. 4(d), boron ions, for example, are implanted into the entire surface in a self-aligned manner at a depth of about I.times.10.times.3 cm.sup.-2. At this time, the third insulating film 6 on the side wall of the recess is
The channel stopper layer 7, which serves as an injection blocking film, is formed only at the bottom of the recess.

Then, as shown in Figure 1(e), by thermal diffusion method,
A channel stopper Fi7 is diffused to a depth of about 1 μm and overlapped with the semiconductor substrate 1.

This method can be achieved, for example, by heat treatment at 1100° C. for about 100 minutes.

Thereafter, as shown in FIG. 1(f), the oxide film serving as the third insulating film 6 on the side wall portion is removed by solution etching using, for example, a hydrofluoric acid solution.

Next, as shown in FIG. 1(g), using the second insulating film 5 as a mask, oxidation is performed, for example, by high-pressure oxidation, to form a fourth insulating film 8 having a thickness of approximately 1.5 μm.

After that, after removing the second insulating film 5 and the second insulating film 5, as shown in FIG.
Ions are implanted and diffused to a depth of about I.times.10"cm@-2 to form a P-type base N9 with a depth of about 0.57 zm.

As described above, according to this embodiment, before the ion implantation of the channel stopper, the side wall of the recess for forming the isolation region is covered with an insulating film, and is used as an implantation blocking film during ion implantation. By doing so, it is possible to suppress the lateral diffusion of the channel stopper, thereby preventing the channel stopper layer from coming into contact with the N-type buried layer and base layer that serve as collectors of the bipolar transistor built in the element region. For example, the bonding between collector boards is
Conventional approximately 50fF per bipolar transistor
It is possible to reduce it by about 60% from about 30 fF to about 30 fF, and the high frequency characteristics of the bipolar transistor can be improved.

Effects of the Invention As described above, the present invention provides a third w! By covering the channel stopper with an edge film and suppressing lateral diffusion of the channel stopper, the collector-substrate and base-collector junction capacitances can be reduced, making it possible to increase the speed of bipolar transistors.

[Brief explanation of the drawing]

1(a) to (h) are step-by-step sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to (h) are
c) is a process cross-sectional view of a conventional method for manufacturing a semiconductor device. 2... N-type buried layer, 3... epitaxial layer, 5...
... Second insulating film, 6... Third insulating film, 7... Channel stopper layer, 8... Fourth insulating film, 9... P-type base layer, 10... Channel stopper lateral direction diffusion layer,
S... Frontage.

Claims (1)

[Claims] selectively forming a second conductivity type buried layer in a first conductivity type semiconductor substrate; forming an epitaxial layer on the semiconductor substrate and the buried layer; and forming a first conductivity type buried layer on the epitaxial layer. a step of laminating an insulating film and a second insulating film;
selectively etching the first and second insulating films to form an opening; etching the epitaxial layer exposed in the opening to form a recess; forming a third insulating film covering the film and the recess, leaving the third insulating film only on the sidewalls in the recess, and forming a channel stopper layer only on the bottom of the recess in a self-aligned manner. After forming and overlapping with the first conductivity type semiconductor substrate,
A method for manufacturing a semiconductor device, comprising: removing the third insulating film; and selectively forming a fourth insulating film in the recess using the second insulating film as a mask.