JPH031546A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To manufacture a high output field effect transistor in which a leakage current from a gate is sufficiently reduced and which is operated in a radio frequency band by a method wherein AlAs thin films and InAs thin films are alternately built up on an InP current channel layer and the ratio between the thicknesses of the adjoining AlAs thin film and InAs thin film is gradually reduced toward the upper layer. CONSTITUTION:A high resistance InP buffer layer 2 and an InP active layer 3 are built up on a semi-insulating InP substrate 1 by an organometal vapor growth method. A source electrode 6 and a drain electrode 7 are provided with a superlattice 4 composed of layers of InAs thin films and AlAs thin films. A current between the source electrode 6 and the drain electrode 7 is controlled by a gate electrode 5 through the superlattice 4. The superlattice 4 is composed of InAs layers 8 and AlAs layers 9 which are alternately built up on the InP active layer 3 by an organometal vapor growth method. Ten layers of the AlAs layers 9 and then layers of InAs layers 8 are built up in such a manner that a ratio between the thicknesses t1 and t2 of the AlAs layer 9 and the InAs layer 8 which are built up on the InP active layer 3 first is t1/t2=0.52/9.48 1.08 and the ratio t1/t2 is gradually reduced toward the upper and t1/t2=6(A)/94(A) 0.064 in the uppermost layer which is brought into contact with the gate electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a field effect transistor using a compound semiconductor, and more particularly to a field effect transistor having a betero junction with an InP current channel layer.

Conventional technology InP is a compound semiconductor that has characteristics such as an electron saturation velocity faster than GaAs, high thermal conductivity, and a small impact ionization gradient, and has high-speed, high-output electric field effects in high frequency bands. Since it is a semiconductor material suitable for transistors (hereinafter referred to as FETs), many structures of FEs have been developed.
T is being attempted.

Problems to be Solved by the Invention However, the Schottky barrier bite between metal and InP is usually as low as 0.3 to 0.4 eV (and it is said that the Schottky junction gate FET that has been put into practical use with GaAs has a large gate leakage current). There are challenges.

Furthermore, in the metal/insulator/semiconductor (old S) FET structure, there is no suitable insulator with a low density of interface states at the interface between InP and the insulator, and no old 5FET with good characteristics has been made to date.

In, A11-XA5 (x = 0.52) has a lattice match with InP and can be easily epitaxially grown on InP using the well-known molecular beam epitaxial growth method (hereinafter referred to as 14BE method), so it can be undoped. InXAl
□-, As(x-0,52) is InP Mis FET
It has the potential to be used as a gate insulating layer. However,
When the mixed crystal ratio X is x=0.25, the Schottky barrier bite is only about 0.8 eV, and the leakage current is too large to be used as a gate insulating layer.

In recent years, in order to solve this problem, In, A I 1-x
An InP MIS FET with a high Schottky barrier bite by reducing the As mixed crystal ratio X to x = 0.43 has been reported (C, M, HANSON et al.,
IEEE Electron DeviceLett
ers, EDL-8, P5:3-54.1987>
.

However, in this case, InP and InxA11-xA
s (x: 0.43) becomes a lattice mismatch, and InP and In
At the hetero interface with XA I 1- and As, dislocation defects are generated in the crystal due to the difference in lattice constant, and fluctuations and instability of FET characteristics become a new problem.

The present invention has been made in view of the above-mentioned conventional situation,
Accordingly, an object of the invention is to provide a novel field effect transistor that makes it possible to solve the above-mentioned problems inherent in the conventional technology.

Differences between the invention and the prior art In contrast to the above-mentioned conventional InP FET, the present invention has the following points:
Thin films of InAs and AlA are used as gate insulating layer materials that do not cause dislocation defects in the crystal at the interface with InP and have a Schottky barrier bite that is high enough to be used in high-power FETs.
The difference is that a superlattice in which thin films of s are alternately laminated is used.

Means for Solving the Problems In order to achieve the above object, a field effect transistor according to the present invention has a current channel layer made of InP, and AlAs thin films and InAs thin films are alternately laminated on the current channel layer,
The film pressure (l) of the adjacent AlAs and the film pressure L2 of the InAs
The ratio tz/l+ decreases toward the upper layer.

) 4BE method or metal organic chemical vapor deposition method (hereinafter referred to as MOCVD)
By using the method, compound semiconductor thin films with different lattice constants are stacked alternately to a thickness that does not exceed the critical film thickness at which dislocation defects begin to occur in the crystal, and dislocation defects are created in the thin films. In recent years, it has become clear that it is possible to stack layers and epitaxially grow without generation.

Using this fact, InA with a difference in lattice constant of about 7%
Even thin films of S and AlAs can be alternately stacked without generating dislocation defects if the thickness is about 25 mm or less. In addition, InJ I 1-XA, which is lattice matched to InP
The In composition X of S is x=0.52, but this In, A
Compound semiconductors equivalent to l1-11As are InAs and Al.
It can be made of a superlattice in which As thin films are alternately laminated. That is, the ratio tr/h of the thickness tl of the InAs thin film to the thickness L2 of the AlAs thin film is 0.5210.48#1.0
8, the superlattice made by stacking these alternately is Ing,
52caO4BAs, and its average lattice constant can be considered to match that of InP. Therefore, if this superlattice is grown on the InP layer that is the current channel layer of the InP old SFET, it is possible to prevent misfit dislocations from occurring at the interface between the InP layer and the superlattice.

Then, by gradually decreasing t+/12 in this superlattice, that is, by decreasing the proportion of InAs thin film, the average bandgap of the superlattice increases, and therefore the Schottky barrier bite with the metal gate electrode is It can be freely increased up to about 1.2 ■.

Embodiments Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of a field effect transistor according to the present invention.

This example describes an InP film using an InP active layer grown by a well-known organometallic vapor phase epitaxy method as a current channel.
This was carried out using Mis FET.

As shown in Figure 1, the plane orientation (100) with added Fe
On a semi-insulating 1nP substrate 1, a high-resistivity InP buffer layer 2 of approximately 11 mm thickness and a 3,000 nm thick InP active layer 3 doped with S at a concentration of 2X10''c+o-3 are deposited in an organometallic vapor phase. The source IC 16 and the drain electrode 7 are made of an AuGeNi alloy, and are layered on the InP active layer 3 in this order.
They are arranged across a superlattice 4 made of laminated S thin films, and are electrically in ohmic contact with the rnP active layer 3.

On the superlattice 4 is a gate electrode 8i! formed of A1! 5 is arranged, thereby connecting the source electrode 6 and the drain electrode ! through the superlattice 4. Control the current between 7.

FIG. 2 is a cross-sectional view showing the structure of the superlattice 4 in detail.

As shown in FIG. 2, the superlattice 4 is formed by growing InAs layers 8 and AlAs layers 9 alternately on the InP active layer 3 using metal organic vapor phase epitaxy. The InAs layer 8 was made from arsine and trimethylindium, and the AlAs layer 9 was made from arsine and trimethylaluminum. I
Thickness L2 of the first AlAs layer 9 in contact with the nP active layer 3 and thickness L of the InAs layer 8 in contact with the AlAs layer 9
The ratio Lt/12 of l is the lattice constant of InP and this AlAs
Since the average lattice constants of layer 9 and InAs layer 8 match, L
1/12: 0.5210.48'; 1.08. Furthermore, Ll.

The thickness of L2 was set to 26 and 24, respectively, to prevent misfit dislocation from occurring at each interface. After that, when the upper AlAs layer 9 and InAs layer 8 are divided into two adjacent layers, the sum of the film thicknesses of each two layers becomes 50, and the tl/lz gradually decreases as the upper layer becomes higher. becomes smaller, and at the top in contact with the gate electrode 5, t, +/1
AlA so that z = 6 (λ) / 94 (human) technique a64
There were 10 S layers and 10 InAs layers 8 each.

In the above InP Mis FET structure, the Schottky barrier bite of the gate electrode 5 and the superlattice 4 is approximately 1 eV, and the leakage current of the gate electrode is Ino, 52AI (,
Compared to the case where 4sAs was used instead of the superlattice 4, the amount decreased significantly, and good high-output FET characteristics were obtained.

FIG. 3 is a sectional view showing a second embodiment of a field effect transistor according to the present invention.

Referring to FIG. 3, in the example of Mizui 2, ion implantation is used to form the current channel layer of the FET, and molecular beam epitaxy is used to form the superlattice consisting of a thin film of 1nAs and AlAs as the gate insulating layer. The law was used.

First, semi-insulating In with plane orientation (100) doped with Fe
St is implanted as an n-type impurity into the P substrate 1 with an energy of 70
Ions are implanted at a dose of 4 x 10!2 cm-'' at eV, and a 5 in 2 film is grown as a heat-treated protective film on the surface of the semi-insulating InP substrate 1 to a thickness of 2,000 cm using a well-known thermal CVD method. Heat treatment was performed at a temperature of 700° C. for 15 minutes in an H 2 atmosphere to form an ion implantation layer 10 that would become a current channel layer with n-type conductivity.

Next, 5 in2 of the heat-treated protective film is removed, and the same superlattice 4 as in the first embodiment is formed using the well-known molecular beam epitaxy method using metals In, Al, and As as raw materials.

The source electrode 6, the drain electrode 7 and the gate electrode 5 are the first
This is the same as the embodiment.

In the InP Mis FET formed according to the above, the Schottky barrier bite of the gate electrode 5 and the superlattice 4 is approximately 1 eV as in the first embodiment, and this actual MAP
Good high-output FET characteristics were also obtained in A.

As described in detail, according to the present invention, a superlattice that is lattice matched with InP on the surface in contact with InP of the current channel layer and has a sufficiently large Schottky barrier bite with the gate ti is formed using InAs and AlAs. By forming thin films alternately stacked and using this as the gate insulating layer of the old S FET, dislocations will not occur at the interface between InP and the superlattice (and the leakage current of the FET gate electrode will be sufficiently reduced). Therefore, it is possible to easily manufacture a high-output field effect transistor that operates in a high frequency band that can fully exhibit the unique electrical characteristics inherent to InP.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a field effect transistor according to the present invention, FIG. 2 is a cross-sectional view showing the structure of the superlattice 4 in FIG. 1 in detail, and FIG. FIG. 3 is a cross-sectional view showing a second embodiment of the field effect transistor according to the invention. 1... Semi-insulating 1nP substrate, 2... High purity InPn
Brim 1, 3... InP active layer, 4... superlattice, 5... gate electrode, 6... source electrode, 7...
・Train electrode, 8...InAs layer, 9...AlA
S layer, 10...Ion implantation layer Patent applicant: NEC Corporation Representative: Patent attorney: Yutabe Kumagai

Claims (1)

[Claims] InP is used as a current channel layer, and A is placed on the current channel layer.
lAs thin films and InAs thin films are laminated alternately, and the ratio t of the film thickness t_1 of the adjacent AlAs and the film pressure t_2 of the InAs is
A field effect transistor characterized in that _2/t_1 decreases toward the upper layer.