JPH03155665A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To form a large capacitance region, to improve the degree of integration and to obtain a large capacitance value even when the area of a memory cell is reduced by mutually shaping each memory cell region in a stratiform shape. CONSTITUTION:An Si island 3 is formed by oxide-film buried insulating isolation films 19a, 19b in a substrate 1, and one Si island is composed of two memory cells, a first memory cell 4 as a lower layer capacitance and a second memory cell 5 as an upper layer capacitance. The storage node electrode 6 of the first memory cell 4 is passed through sections just over the word electrode 13a of the first memory cell 4 and the contact region of a charge transfer line 15 and an impurity diffusion region 14 from the contact region (corresponding to the region of an Si pad 18a) of the first memory cell 4, extended up to a section just above the word electrode 13b of the second memory cell 5, and also extended to a section just above the isolation region 19a with a memory cell adjacent to the first memory cell 4. On the other hand, the storage node electrode 7 of the second memory cell 5 is elongated similarly up to a section just over the word electrode 13a of the first memory cell 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a dynamic random access memory (hereinafter referred to as DRAM).

(Prior Art) FIG. 8 is a front sectional view showing the cell structure of a conventional stacked DRAM, in which 51 is a storage node electrode, 52
53 is a cell plate which is an electrode, 53 is a capacitive insulating film, 54 is a switching transistor, 55 is a gate electrode, 56 is a source region, and 57 is a bit line.

In the figure, charges are stored in a capacitor made up of a storage node electrode 51, a cell plate 52, and a capacitor insulating film 53 sandwiched between these electrodes 51 and 52.

and the gate electrode 55 of the switching transistor 54.
Due to the voltage applied to the switching transistor 5
4 is on (ON) L, the charge accumulated in the storage node electrode 51 flows to the bit line 57 via the source region 56 and the gate electrode 55, and information is written.

Enable reading.

Figure 9 shows one of the conventional stacked trench DRAMs, “ISOLATION-MERGED VERTI”.
6 is a front cross-sectional view showing the cell structure of "CAL CAPACITOR (IVEC)", in which 61 is a trench, 62 is a storage node electrode, 63 is a cell plate which is an electrode;
4 is a capacitive insulating film, 65 is a switching transistor, 6
6 is a gate electrode, 67 is a source region, and 68 is a bit line.

In the figure, charges are stored in a capacitor consisting of a storage node electrode 62 and a cell plate 63 formed on the side of a trench 61, and a capacitor insulating film 64 sandwiched between these electrodes 62 and 63. , the switching transistor 65 is turned on by the voltage applied to the gate 111[166 of the switching transistor 65, and the charge accumulated in the storage node electrode 62 is transferred to the source region 67.
and flows to the bit line 68 via the gate electrode 66, making it possible to write and read information.

The memory cell configured as described above has one cell on one Si island, and the capacitor is formed on the side wall of the Si island 69. Therefore, it becomes possible to obtain a large capacity with the shallow trench 61.

However, as DRAMs become more highly integrated, the area of memory cells becomes smaller, and the planar dimension of the capacitor region also becomes smaller.

Therefore, as in the conventional stack type DRAM mentioned above, a capacitance is formed between layers or on the side wall portion, or as in a trench type DRAM, a capacitor is formed on the side wall of a groove formed in a Si substrate. Efforts have been made to obtain a capacitance value of more than
acked CapacitorCells for
High-density dynamic RAM5
”IEDM Digest of Technical Papers (IEDM Dig, of Tech, paper)
rs) 1988 p. 600, and for trench type DRAMs, Shigeru Nakaji
ma et al.: “An Isolati
onMerged Vertical Capacit
or Ce1l For LargeCapacity
DARM” IEDM Digest of Technical Babers (IEDM Dig, of Tech.

papers) 1988 p. 240. ) (Problem to be Solved by the Invention) In the above-mentioned conventional technology, in the case of a stacked DRAM, as the area of the memory cell becomes smaller, the space between the eyebrows, which forms a capacitance,
Since the area of the side wall portion also becomes smaller, the capacitance value also becomes smaller. Therefore, reducing the thickness of the capacitor insulating film or using an insulating film with a high dielectric constant may be considered, but this is currently difficult to achieve due to reliability and other reasons.

Furthermore, in the IVEC-DRAM, when the area of the memory cell is reduced, it becomes necessary to form a deep trench in order to ensure a capacitance value greater than a certain value, which poses a problem in that it is difficult to manufacture.

A first object of the present invention is to provide a semiconductor memory device that can secure a capacitance value similar to the conventional one while ensuring a higher degree of integration. The objective is to provide a semiconductor memory that can ensure the following.

(Means for Solving the Problems) In order to achieve the above-mentioned first object, a first means of the present invention provides that each capacitance region of a plurality of memory cells is A multilayer structure is formed above the substrate so as to mutually include the capacitance regions of the memory cells, and further, in claim (1), the capacitance region has a structure formed in parallel to the surface of the substrate. Then, the first capacitance, which is the lowest layer capacity,
In the memory cell, the active region of the first memory cell and the active region of the adjacent second memory cell except for the contact portion between the storage node of the second memory cell and the impurity diffusion region of the switching transistor; The second memory cell, which includes a part of the isolation region between the memory cell and the second memory cell and is an upper layer capacitor, has an active region of the second memory cell and a part of the isolation region between the first memory cell and the second memory cell. and a region excluding a contact region between the storage node and the impurity diffusion region from the active region of the adjacent first memory cell, further comprising: The capacitor region has a structure formed in parallel to the substrate surface, and in the first memory cell which is the lowest layer capacitor, a part of the active region of the first memory cell and the active region of the adjacent second memory cell , a region excluding the contact portion between the storage node of the second memory cell and the impurity diffusion region of the switching transistor, a part of the separation region between the first memory cell and the second memory cell, and the opposite side of the first memory cell. In the second memory cell, which includes a part of the isolation region of adjacent memory cells and is an upper layer capacitor, part of the active region of the second memory cell and the isolation region of the first memory cell and the second memory cell and a region excluding a contact region between a storage node and an impurity diffusion region from an active region of an adjacent memory cell on the opposite side, further comprising: The capacitor region has a structure formed in parallel to the substrate surface, and in the first memory cell which is the lowest layer capacitor, the active region and part of the isolation region of the first memory cell and the adjacent second memory cell The second memory cell, which is an upper layer capacitor, includes a part of the active region of the cell, a part of the isolation region, and a part of the active region and part of the isolation region of the adjacent memory cell on the opposite side. The storage node of the second memory cell connects the storage node of the first memory cell to the storage node of the first memory cell.
In a third memory cell which has a shape parallel to the contact position of the second memory cell rotated 180 degrees around the substrate contact and is the uppermost layer capacitor, the storage node of this third memory cell is connected to the first memory cell. The present invention is characterized in that the storage node of the memory cell is configured to have a shape parallel to the position of the third memory cell.

Further, in order to achieve the above-mentioned second object, the second means of the present invention is to form a plurality of trenches in a semiconductor substrate of one conductivity type, and to form a plurality of trenches between the trenches, as described in claim (5). A plurality of memory cell regions are provided on the Si island, and
A laminated capacitive region is provided on the side wall of the island so that the capacitive region of one memory cell and the capacitive region of another memory cell mutually extend, and further characterized in that the Si It is characterized in that the bit line is in contact with one location of the impurity diffusion region on the island surface.

(Function) According to the first means, since each memory cell region is formed in a layered manner, in the case of a stacked DRAM, compared to one in which a capacitor is formed in a memory cell region on a plane, , a large capacitance value can be achieved even if the memory cell area is small.

Further, according to the second means, in the case of a trench-type DRAM, the capacitance region of one memory cell and the capacitance region of another memory cell formed in a stacked manner on the side wall of the Si island mutually extend. Therefore, even if the memory cell area becomes smaller, a constant capacitance value can be achieved without forming a deep trench.

(Example) Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a front sectional view of a first embodiment of the present invention, FIG. 2 is a plan view of the first embodiment, and FIG. 1 is a sectional view taken along line AA' in FIG.

In the figure, l is a one-conductivity type semiconductor substrate, 3 is a Si island,
4 is a first memory cell, 5 is a second memory cell, and 6 and 7 are storage node electrodes forming a capacitor (in FIG. 2,
8 and 9 are switching transistors; 10 and 11 are source regions; 12 is a cell plate forming a capacitance region; 13a is a gate electrode of the first memory cell 4 (word line 13b is a gate electrode of the second memory cell 5, 14 is a drain (impurity diffusion region), 15 is a bit line which is a charge transfer line, 16.16
a and 16b are polycrystalline SL pads, 17 is a nitride film, 18 is a capacitor insulating film, 19a and 19b are oxide film-embedded insulating isolation films that serve as isolation regions, 20 is a storage node/substrate contact, 21 is an H2O layer, 22 is the BPSG layer.

In FIG. 1, charges are stored on storage node electrodes 6 and 7.
The energy is stored in the capacitance of the capacitive region formed by the cell plate 12 and the capacitive insulating film 18 sandwiched between these electrodes 6°7.12.

The substrate 1 has Si islands 3 formed by oxide-buried insulating isolation films 19a and 19b, and one Si island 3 has two memory cells, that is, a first memory cell 4 serving as a lower layer capacitor.
and a second memory cell 5 serving as an upper layer capacitor.

The storage node electrode 6 of the first memory cell 4 extends from the contact region (corresponding to the Si pad 18a region) of the first memory cell 4 to the word electrode 13a of the first memory cell 4.
, passing directly above the contact region between the charge transfer line 15 and the impurity diffusion region 14, extending to directly above the word electrode 13b of the second memory cell 5, and further separating the first memory cell 4 from the adjacent memory cell. It also extends directly above 19a.

On the other hand, the storage node electrode 7 of the second memory cell 5 is
Contact region of second memory cell 5 (Si pad 18b
) to the word electrode 13b of the second memory cell 5, the contact area between the charge transfer line 15 and the impurity diffusion region 4, and the first
It extends directly above the word electrode 13a of the memory cell 4, and further extends directly above the isolation region 19b from the memory cell adjacent to the second memory cell 5, and overlaps with the storage node electrode 6.

Said 1st. The capacitive insulating film 18 of the second memory cells 4 and 5 is
Although it is formed using an oxynitride film, it may be formed using a high dielectric constant film such as Ta, O, or the like.

Note that the interlayer film includes an HTO layer 21 formed by a CVD method.
．． A BPSG layer 22 was used.

The word electrodes @13a and 13b have a silicide/polysilicon structure and have a film thickness of 0.25-. The charge transfer line 15 is made of polysilicon and has a film thickness of 0.2
It is 5-. Furthermore, the storage node electrode 6.7 and the cell plate 12 are formed of polysilicon,
The film thickness is 0.14. In FIG. 2, the design dimensions (second
) is 0,40PXO04o4, word line 1
The width of the charge transfer line 15 is 0.4 m, and the minimum width of the element isolation portions 19a and 19b is 0.4 m, and the area of the memory cells 4 and 5 is 0.4 m. S is 1
．． In FIG. 2, the storage node electrode 6 of the first memory cell 4 is indicated by a - dotted line, and the second
The storage node electrode 7 of the memory cell 5 is indicated by a two-dot chain line. In addition, the area C surrounded by short diagonal lines is the activation area (
11, 14).

The cell capacity of the first example was 38 fF, assuming that the oxide film equivalent value of the oxynitride film was 5 layers m.

FIG. 3 is a plan view showing an example in which the mask shape of the storage node area in the first embodiment is changed.

In the same figure, if each storage node electrode 6.7 is changed to the rectangular shape shown in the figure, the proximity effect between patterns can be further suppressed during lithography and dry etching during storage node formation, and 256 Mbit, I Gb
It is valid for IT level products.

In FIG. 3, a region C' surrounded by short diagonal lines is an active region (corresponding to the source region 11 and drain 14 in FIG. 1). Also, in a certain column, a first memory cell 4a
, a second memory cell 5a are arranged, and a first memory cell 4b and a second memory cell 5b are arranged in the upper and lower columns adjacent to the specific column.

When the bit line capacitance (CI) in the structure of the first embodiment (Fig. 2) was calculated, as shown in Table 1,
64 divisions, each division (equivalent to 256 bits), 99,
Table 1 shows the specific breakdown of C3. The storage node electrodes 6 and 7 cover the bit line 15, and the capacitance value (51, 2fF) between them is 5.
It accounts for 2%. The values of the counter word electrode, counter substrate, and counter field oxide film are shown in Table 1, and from Table 1, this structure is 6
It is considered that this method is fully applicable to 4M DRAM and later.

Table 1 FIG. 4 is a plan view of the second embodiment of the present invention, in which only the storage node area is shown for the activation region C'', and this second embodiment is similar to the first embodiment. This is a stacked DRAM in which three adjacent memory cells (first memory cell 4, second memory cell 5, third memory cell 2)
The storage node electrodes 6 (-dashed line), 7 (two-dot chain line), and 24 (thin broken line) of 3) are each formed of conductors of different layers. In this second embodiment, all three layers of storage node electrodes 6, 7.24 are formed of polysilicon. 25 in the figure is a storage node/substrate contact.

In the second embodiment, in the first memory cell 4 which is the lowest layer capacitor, the active region and part of the isolation region of the first memory cell 4 are separated from the part of the active region of the adjacent second memory cell 5. In the second memory cell 5 which is an upper layer capacitor and includes a part of the region, a part of the active region of the adjacent memory cell on the opposite side, and a part of the isolation region, the storage node of the second memory cell 5 The electrode 7 rotates the storage node electrode 6 of the first memory cell 4 by 180 degrees around the storage node/substrate contact 25 of the first memory cell 4, and
The third memory cell 23 has a shape that has been moved to the position of the contact 25 of the memory cell 5, and is the uppermost layer capacitor.
Then, the storage node electrode 24 of the third memory cell 23 is the storage node electrode 6 of the first memory cell 4.
is configured to have a shape that is translated in parallel to the position of the third memory cell 23.

When the area of the memory cell is 0°74" (corresponding to 256MdRAM), the structure of the first embodiment has a capacity of 21f.
However, in the structure of the second embodiment, it becomes 36 fF.

FIG. 5 shows the relationship between cell capacitance and memory cell area in the structure of a conventional DRAM and the structure of the first and second embodiments of the present invention.

The two-layer structure in the figure corresponds to the first embodiment in which the storage electrode has two layers, and the three-layer structure in the figure corresponds to the second embodiment in which the storage electrode has three layers. solid line.

The broken line is a simple calculation result when the thickness of the capacitive insulating film is 6 m, and the plots in the figure are actually measured values. The structure of the second embodiment can fully accommodate up to 256 MDRAMs within the scope of the concept of the present invention.

6 is a front sectional view of the third embodiment of the present invention, FIG. 7 is a plan view of the third embodiment, and FIG. 6 is a sectional view taken along the line BB' in FIG. 7.

In the figure, 31 is a semiconductor substrate of one conductivity type, 32 is a trench, 33 is a Si island, 34 is a first memory cell, 35 is a second memory cell, 36.37 is a storage node electrode forming a capacitance region, 38. 39 is a switching transistor; 40.41 is a source region; 42 is a contact region between the source region 40 and storage node electrode 36; 43 is a contact region between source region 41 and storage node electrode 37;
4 is a cell plate forming a capacitive region, 45a is a gate electrode of the first memory cell, 45b is a gate electrode of a second memory cell, 46 is a drain (impurity diffusion region), 47 is a bit line, and 48 is a polycrystalline Si pad. , 49 indicates a capacitive insulating film.

In FIG. 6, a plurality of trenches 32 are formed in a substrate 31 to form a large number of Si islands 33, and one Si island 3
There are two memory cells on 3, namely the first memory cell 3
4 and a second memory cell 35 are formed.

a storage node electrode of the first memory cell 34;
In the trench 32 portion, the source region 4° of the switching transistor 38 of the first memory cell 34 and the Si
The island 33 is in contact with the upper contact area 42 of the side wall, and the seventh
As shown in the figure, it is formed to surround the side wall of the Si island 33. However, the storage node electrode 36 is not formed on the source region 41 of the second memory cell 35 and the contact region 43 on the sidewall of the Si island 33.

On the other hand, the storage node electrode 37 of the second memory cell 35
is the switching transistor 3 of the second memory cell 35
The source region 41 of No. 9 contacts the upper contact region 43 of the side wall of the Si island 33, surrounds the entire side wall of the Si island 33, and connects to the capacitive region (storage node electrode 36 and cell plate 44) of the first memory cell 34. They are formed to overlap and extend.

Therefore, a stacked capacitor is formed in the trench 32 portion of the side wall of the Si island 33 by the storage node electrodes 36 and 37 and the cell plate 44.

Said 1st. Cell plate 4 of second memory cell 34.35
4 is shared by polysilicon.

Further, the bit line 47 is in contact with the surface of the impurity diffusion region 46 between the gate electrodes 45a and 45b of the switching transistors 38 and 39 of the first memory cell 434 and the second memory cell 35.

In addition, 1. In both of the second memory cells 34 and 35, the capacitor insulating film is formed of an oxynitride group, and has a thickness of 5 in terms of oxide film.

The planar design dimensions of each part are explained with reference to Fig. 7.
The dimensions of word lines (common with gate electrodes) 45a and 45b are 0.4/ffi, and the dimensions of word lines 47 and impurity diffusion regions 46 are 0.4/ffi.
The contact dimensions are 0.5 ina x 0.4 mm, the separation width is 0.9-'', and the memory cell area is 1.6-''.

Note that the thicknesses of the storage node electrodes 36 and 37 and the cell plate 44 in FIG. 7 are 0.1-. In addition, the capacitance value is determined by setting the depth of trench 2 to 1.1- and the capacitance oxide film to 5n.
If m, 45 fF can be obtained.

In addition, 1. The manufacturing method in the second embodiment is that after the storage node electrodes 6, 7.24 are buttered, the storage node oxide film is removed using a concentrated acid-based aqueous solution using the nitride film as a stopper.
,7.24.

(T, Ema et al.: IEDM Digest of Technical Babers (rEDM Dig
, of Tech.

papers) 1988 p., 592-595)
Further, the manufacturing method in the third embodiment of the structure of the present invention is r
The manufacturing method of VE・C was used as a reference.

(S, Nakajima et al.: IEDM
Dig, of Tech.

p, 240.1987) (Effects of the Invention) As explained above, according to the first means of the present invention, each memory cell region is formed in a layered manner with respect to the conventional memory cell. If the planar dimension is , it can have a large capacity area, and the degree of integration becomes large
It is possible to provide a semiconductor memory device that can obtain a large capacitance value even if the memory cell area is reduced, and according to the second means, it is possible to provide a semiconductor memory device that can obtain a capacitance value of a certain value or more even in a shallow trench. .

[Brief explanation of the drawing]

FIG. 1 is a front sectional view of the first embodiment of the present invention, FIG. 2 is a plan view of the first embodiment, and FIG. 3 is a plan view showing an example in which the mask shape of the storage node area in the first embodiment is changed. 4 is a plan view of the second embodiment of the present invention, FIG. 5 is an explanatory diagram showing the relationship between cell capacity and memory cell area, and FIG. 6 is a front sectional view of the third embodiment of the present invention. FIG. 7 is a plan view of the third embodiment, FIG. 8 is a front sectional view of a conventional stacked DRAM, and FIG. 9 is a front sectional view of a conventional stacked drain DRAM. 1.31... One conductivity type semiconductor substrate, 3,33...
Si island, 4,34...first memory cell, 5.35
...Second memory cell, 6, 7, 24° 36, 37.
...St 1 node electrode, 8゜9, 38.39
...Switching transistor, 10.11.40
．． 41... Source region, 12... Cell plate,
13a, 13b, 45a. 45b... Gate electrode, 14.46... Impurity diffusion region, 15.47... Bit line, 16° 16a, 1
6b, 48-" polycrystalline Si pad, 17... Nitride film, 18.49... Capacitive insulating film, 19a,
19b... Oxide film buried insulating isolation film, 20... Storage node/substrate contact, 21... HTO layer,
22...BPSG layer, 23 River third memory cell, 42°43... Contact area.

Claims (6)

[Claims] (1) A semiconductor memory device characterized in that multiple layers are formed above a substrate so that each capacitance region of a plurality of memory cells mutually includes a capacitance region of another memory cell. (2) The capacitor region has a structure formed in parallel to the substrate surface, and in the first memory cell which is the lowest layer capacitor, the active region of the first memory cell and the active region of the adjacent second memory cell The region includes a region excluding the contact portion between the storage node of the second memory cell and the impurity diffusion region of the switching transistor, and a part of the isolation region between the first memory cell and the second memory cell, and the upper layer capacitance is In the second memory cell, a storage node and an impurity diffusion region are formed from the active region of the second memory cell, a part of the isolation region between the first memory cell and the second memory cell, and the active region of the adjacent first memory cell. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a region other than a contact region. (3) The capacitor region has a structure formed in parallel to the substrate surface, and in the first memory cell, which is the lowest layer capacitor, a part of the active region of the first memory cell and an adjacent second memory cell A region excluding a contact portion between the storage node of the second memory cell and the impurity diffusion region of the switching transistor from the active region of the cell, a part of the isolation region between the first memory cell and the second memory cell, and the first memory cell. The second memory cell, which is an upper layer capacitor, includes a part of the isolation region of the adjacent memory cell on the opposite side, and includes a part of the active region of the second memory cell, the first memory cell, and the second memory cell. Claim (1) characterized in that the storage node is configured to include a part of the isolation region and a region excluding the contact region between the storage node and the impurity diffusion region from the active region of the adjacent memory cell on the opposite side. The semiconductor memory device described above. (4) The capacitor region has a structure in which it is formed in parallel to the substrate surface, and in the first memory cell which is the lowest layer capacitor, the active region and part of the isolation region of the first memory cell are adjacent to each other. a part of the active region and a part of the isolation region of the second memory cell;
In the second memory cell, which includes a part of the active region and a part of the isolation region of an adjacent memory cell on the opposite side and is an upper layer capacitor, the storage node of the second memory cell is connected to the storage node of the first memory cell. The node is rotated 180 degrees around the storage node/substrate contact of the first memory cell and translated in parallel to the contact position of the second memory cell. 2. The semiconductor memory device according to claim 1, wherein the storage nodes of the three memory cells have a shape obtained by moving the storage node of the first memory cell in parallel to the position of the third memory cell. (5) forming a plurality of trenches in one conductivity type semiconductor substrate;
A plurality of memory cell regions are provided on the Si island formed between the trenches, a stacked capacitor region is provided on the side wall of the Si island, and the capacitor region of one memory cell and the capacitor region of another memory cell mutually extend. A semiconductor memory device characterized in that it is configured as follows. (6) The semiconductor memory device according to claim (5), characterized in that the bit line is in contact with one location of the impurity diffusion region on the surface of the Si island.