JPH03157624A - Production of thin-film transistor - Google Patents

Production of thin-film transistor

Info

Publication number
JPH03157624A
JPH03157624A JP1296903A JP29690389A JPH03157624A JP H03157624 A JPH03157624 A JP H03157624A JP 1296903 A JP1296903 A JP 1296903A JP 29690389 A JP29690389 A JP 29690389A JP H03157624 A JPH03157624 A JP H03157624A
Authority
JP
Japan
Prior art keywords
film
electrodes
resist
gate
opaque
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1296903A
Other languages
Japanese (ja)
Inventor
Norio Nakatani
中谷 紀夫
Terushi Sasaki
昭史 佐々木
Keizo Yoshizako
吉迫 圭三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1296903A priority Critical patent/JPH03157624A/en
Publication of JPH03157624A publication Critical patent/JPH03157624A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To simplify the process for production by forming the resist of the reversal patterns of the opaque electrodes of gates-sources and drains by back exposing of a light shielding film and using this resist as a photomask or making self-matching formation by a lift-off method. CONSTITUTION:A gate electrode material consisting of Cr or Au is formed by sputtering on a transparent insulating substrate 1 and the gate electrodes 2 are formed by a photolithography method. A gate insulating film 3 consisting of Si oxide and a semiconductor film 4 consisting of amorphous Si are then formed by a P-CVD method and are patterned by the photolithography method. A transparent conductive film consisting of ITO is then formed by a sputtering method to form display electrodes 5. An Al film is then formed and after the source electrodes and drain electrodes 6 are formed, an insulating film 7 consisting of Si oxide is formed by P-CVD. the semiconductor film 4 is completely covered by the aggregated segments formed continuously with the gate electrodes 2, the source electrode and drain electrodes 6. A negative resist is then applied over the entire surface of the insulating film 7 and is subjected to the back exposing, by which the light shielding film 10 is formed on the aggregated blocks via the resist patterns 9 reversed from the aggregated blocks of the electrodes 2, 6, etc. The TFTs are thus formed.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は薄膜トランジスタ(以下、TPTと称する)、
特にアクティブマトリクス型液晶表示装置用のトランジ
スタアレーに好適なTPTの製造方法に関する。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to thin film transistors (hereinafter referred to as TPT),
In particular, the present invention relates to a method of manufacturing TPT suitable for transistor arrays for active matrix liquid crystal display devices.

(ロ)従来の技術 近年、非晶質半導体膜形成技術の進歩により、同、一基
板上にスイッチング特性が均一なTPTを大量に形成で
きるようになったため、これによるTPTアレーを用い
たアクティブマトリクス型液晶表示装置が実用化されつ
つある。
(b) Conventional technology In recent years, advances in amorphous semiconductor film formation technology have made it possible to form large quantities of TPTs with uniform switching characteristics on the same substrate. type liquid crystal display devices are being put into practical use.

第4図に従来の液晶表示装置用TFTアレーのTFT部
分の断面図を示す。同図のTPTは、ガラス等の透明絶
縁性基板1上に、ゲート電極2、ゲート絶縁膜3、非晶
質半導体111!4、表示電極5、ソース電極並びにド
レイン電極6、絶縁膜7、遮光膜8を順次積層したもの
である。同図の遮光膜8は上記非晶質半導体膜4が光を
受けて、TPTが誤動作するのを防止するために、非晶
質半導体81!4をカバーできる大きさに形成されてい
る(特開昭56−1403211゜ 同図のTPTの製造は、まずガラス等の絶縁性基板の上
にスパッタ法・蒸着法等によりゲート電極材料を形成し
、フォトリソグラフ法等によりゲート電極2を形成する
。次に、その上にゲート絶It膜3、非晶質半導体膜4
をP−CVD法等によフ順次成膜し、7オトリングラフ
法等によりパターン形成する。その後、透明導を膜で表
示電極5を形成してさらに、AI等の金属でソース電極
並びにドレイン電極6を形成し、これら電極が形成され
た基板全面にTPTの保護膜となる絶縁膜7を成膜する
。そして最後に、不透明、即ち非道光性である金属膜等
により光遮蔽膜8を上記非晶質半導体膜4上の位置に形
成する。
FIG. 4 shows a sectional view of a TFT portion of a conventional TFT array for a liquid crystal display device. The TPT shown in the figure has a gate electrode 2, a gate insulating film 3, an amorphous semiconductor 111!4, a display electrode 5, a source electrode and a drain electrode 6, an insulating film 7, and a light shielding film 7 on a transparent insulating substrate 1 such as glass. The film 8 is sequentially laminated. The light shielding film 8 shown in the figure is formed in a size that can cover the amorphous semiconductor 81!4 in order to prevent the TPT from malfunctioning due to the amorphous semiconductor film 4 receiving light (specially To manufacture the TPT shown in the figure, first, a gate electrode material is formed on an insulating substrate such as glass by a sputtering method, a vapor deposition method, etc., and a gate electrode 2 is formed by a photolithography method or the like. Next, on top of that, a gate isolation It film 3 and an amorphous semiconductor film 4 are formed.
are sequentially formed into films by a P-CVD method or the like, and then patterned by a 7-otrin graph method or the like. After that, a display electrode 5 is formed using a transparent conductive film, a source electrode and a drain electrode 6 are formed using a metal such as AI, and an insulating film 7 that becomes a protective film for TPT is formed on the entire surface of the substrate on which these electrodes are formed. Form a film. Finally, a light shielding film 8 is formed on the amorphous semiconductor film 4 using an opaque, ie non-optical, metal film or the like.

(ハ)発明が解決しようとする課組 ヒ述の如き従来のTPTの製造方法では、製造工程が複
雑であるためコストがかかるという問題点が指摘されて
おり、使用するマスク枚数の減少や製造工程の簡略化が
要望されている。
(c) It has been pointed out that the conventional TPT manufacturing method, as described in Section 1, which the invention aims to solve, has the problem of high costs due to the complicated manufacturing process, which leads to a reduction in the number of masks used and There is a demand for process simplification.

本発明はこのような問題点に鑑み、特に遮光膜の製造工
程を簡略化し、かつ高性能なTPTを得ることのできる
製造方法を提供することを課題とするものである。
In view of these problems, it is an object of the present invention to provide a manufacturing method that particularly simplifies the manufacturing process of a light-shielding film and can obtain a high-performance TPT.

(ニ)課題を解決するための手段 本発明のTPTの製造方法は、遮光膜を背面露光に、よ
りゲート・ソース・ドレインの不透FIII電極の反転
パターンのレジストを形成し、該レジストをマスクにし
たリフトオフ法により、ゲート・ソース・ドレインの各
不透明電極が集合したTPT区画に対して自己整合的に
形成するものである。
(d) Means for Solving the Problems The TPT manufacturing method of the present invention involves forming a resist with an inverted pattern of the opaque FIII electrodes of the gate, source, and drain using a light-shielding film as a backside exposure, and using the resist as a mask. By using the lift-off method described above, each opaque electrode of the gate, source, and drain is formed in a self-aligned manner with respect to the assembled TPT section.

(ホ)作用 本発明によれば、自己整合法を使用することによりパタ
ーンニングのマスク枚数を減少させることができ、さら
にリフトオフ法を適用することで工・ノチング工程を省
略できるので、簡単なプロセスで高性能のTPTが作成
可能となり、製造コストの低減を図ることができる。
(E) Function According to the present invention, the number of masks for patterning can be reduced by using the self-alignment method, and furthermore, the etching and notching steps can be omitted by applying the lift-off method, resulting in a simple process. It becomes possible to create a high-performance TPT using this method, and it is possible to reduce manufacturing costs.

(へ)実施例 以下、本発明の実施例について図面を参照しながら説明
する。第1図はTPTの断面図を示し、第2図は平面図
を示すものである。また、第3図(a)〜(d)は工程
順の断面図をしめす。
(F) Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a sectional view of the TPT, and FIG. 2 shows a plan view. Moreover, FIGS. 3(a) to 3(d) show cross-sectional views in the order of steps.

まず、ガラス等の透明な絶縁基板1上にスパッタ法・蒸
着法等によりクロムや金からなるゲート電極材料を形成
し、7オトリソグラフ法等によリゲート電極2を形成す
るU第3図(aN。その上に酸化シリコンあるいは窒化
シリコンにてゲート絶縁膜3、さらにアモルファスシリ
コンからなる半導体膜4をP−CVD法等により順次成
膜し、フォトリングラフ法等によりパターン形成する[
第3図(b)]。この時のパターンニングにより、上記
半導体膜4は上記ゲート電極2上に配置される。
First, a gate electrode material made of chromium or gold is formed on a transparent insulating substrate 1 made of glass or the like by a sputtering method, a vapor deposition method, etc., and a regate electrode 2 is formed by an otolithography method or the like. A gate insulating film 3 made of silicon oxide or silicon nitride and a semiconductor film 4 made of amorphous silicon are sequentially formed thereon by a P-CVD method or the like, and then patterned by a photolithography method or the like.
Figure 3(b)]. By patterning at this time, the semiconductor film 4 is placed on the gate electrode 2.

次に、スパッタ法等によりITO材料からなる透明導電
膜を膜付し、7オトリソグラフ法等により表示電極5を
形成する。その後、スパッタ法・蒸着法等によりAI等
の金属を膜付し、7オトリソグラフ法等によりソース電
極並びにドレイン電極6を形成した後、P−CVD法等
により酸化ジノコンあるいは窒化シリコンなどからなる
絶縁膜7を成膜する[第3図(C)]。この時のソース
電極並びにドレイン電極6は上記半導体1114上に互
いに分離されて設けられ、上記ゲート電極2とはそれぞ
れ一部重なりあう位置関係となるので、ゲート電極2、
及びソース電極並びにドレイン電極6の連続した集合区
画で上記半導体膜4が完全にカバーされる。
Next, a transparent conductive film made of ITO material is applied by sputtering or the like, and display electrodes 5 are formed by 7-otolithography or the like. Thereafter, a film of metal such as AI is applied by sputtering, vapor deposition, etc., a source electrode and a drain electrode 6 are formed by 7 otolithography, etc., and then an insulator made of dinocone oxide or silicon nitride, etc. is formed by P-CVD, etc. A film 7 is formed [FIG. 3(C)]. At this time, the source electrode and drain electrode 6 are provided on the semiconductor 1114 to be separated from each other, and are in a positional relationship that partially overlaps with the gate electrode 2, so that the gate electrode 2,
The semiconductor film 4 is completely covered by the continuous collection section of the source electrode and the drain electrode 6.

次に、ネガレジストを上記絶縁膜7上の全面に塗布し、
背面露光により不透明なゲート電極2、及びソース電極
並びにドレイン電極6の集合区画を反転したレジストパ
ターン9を得る。[第3図(d)]。なお、この際のレ
ジストパターン9の寸法は露光量により制御できる。
Next, a negative resist is applied to the entire surface of the insulating film 7,
By back exposure, a resist pattern 9 is obtained in which the collective sections of the opaque gate electrode 2, source electrode, and drain electrode 6 are reversed. [Figure 3(d)]. Note that the dimensions of the resist pattern 9 at this time can be controlled by the exposure amount.

この後、第3図(d)の如く形成されたレジストパター
ン9とこれから露出した絶縁膜7上に非透光性であるク
ロムなどの金属膜等を成膜し、上記レジストパターン9
をマスクとしたり7トオフ法により不透明なゲート電極
2、及びソース電極並びにドレイン電極6の集合区画に
対して自己整合的に遮光膜10を形成する事によって、
第1図に示す如く遮光膜10を備えたTPTが製造でき
る。なお、この遮光膜10は第2図の平面図に示したよ
うにハツチングされた電極の集合区画をカバーするので
、TPT位置のみならずブラックマトリクマスクのよう
に格子状の画素間隙位置にも配置されることになる。
Thereafter, a non-transparent metal film such as chromium is formed on the resist pattern 9 formed as shown in FIG. 3(d) and the insulating film 7 exposed from the resist pattern 9.
By forming the light-shielding film 10 in a self-aligned manner with respect to the collective section of the opaque gate electrode 2, source electrode, and drain electrode 6 by using as a mask or using the 7-off method,
A TPT equipped with a light shielding film 10 as shown in FIG. 1 can be manufactured. Note that this light-shielding film 10 covers the hatched electrode collection section as shown in the plan view of FIG. 2, so it can be placed not only at the TPT position but also at the grid-like pixel gap positions like a black matrix mask. will be done.

(ト)発明の効果 本弛明のTPTの製造方法によれば、半導体膜をカバー
する遮光膜が背面露光によりゲート・ソース・ドレイン
の不透明電極の反転パターンのレジストを形成し、該レ
ジストをマスクにしたリフトオフ法により、自己整合的
に形成でき、これによって製造工程の簡略化を実現し製
造コストの低減が図れる。しかもこの遮光膜によって半
導体膜を確実に遮光できるので、特にバックライトを用
いた液晶T V用パネルの如く光照射状態で用いる液晶
表示装置用TPTアレーに最適な信頼性の高いTPTを
得ることができる。
(G) Effects of the Invention According to the TPT manufacturing method of the present invention, the light-shielding film covering the semiconductor film forms a resist with an inverted pattern of the opaque electrodes of the gate, source, and drain by back exposure, and the resist is masked. The lift-off method described above enables formation in a self-aligned manner, thereby simplifying the manufacturing process and reducing manufacturing costs. Moreover, since this light-shielding film can reliably shield the semiconductor film from light, it is possible to obtain a highly reliable TPT that is especially suitable for TPT arrays for liquid crystal display devices that are used under light irradiation, such as LCD TV panels that use backlights. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明製造方法で得られるTPTの断面図、第
2図は本発明製造方法で得られるTPTアレーの平面図
、第3図(a)〜(d)は本発明方法を示すTPTの製
造工程順の断面図、第4図は従来のTPTの断面図であ
る。
FIG. 1 is a cross-sectional view of TPT obtained by the manufacturing method of the present invention, FIG. 2 is a plan view of a TPT array obtained by the manufacturing method of the present invention, and FIGS. 3(a) to 3(d) are TPTs showing the method of the present invention. FIG. 4 is a cross-sectional view of a conventional TPT.

Claims (1)

【特許請求の範囲】[Claims] (1)透明な絶縁基板上に不透明なゲート電極と半導体
膜と不透明なソース並びにドレイン電極膜と遮光膜を積
層形成してなる薄膜トランジスタにおいて、前記遮光膜
を背面露光によりゲート、ソース、及びドレインの各不
透明電極の反転パターンのレジストを形成し、該レジス
トをマスクとしたリフトオフ法により、ゲート、ソース
、及びドレインの各不透明電極に対して自己整合的に形
成することを特徴とした薄膜トランジスタの製造方法。
(1) In a thin film transistor in which an opaque gate electrode, a semiconductor film, an opaque source, a drain electrode film, and a light-shielding film are laminated on a transparent insulating substrate, the light-shielding film is exposed to the back side to form the gate, source, and drain. A method for manufacturing a thin film transistor, characterized in that a resist having an inverted pattern of each opaque electrode is formed, and by a lift-off method using the resist as a mask, the opaque electrodes are formed in a self-aligned manner with respect to each opaque electrode of the gate, source, and drain. .
JP1296903A 1989-11-15 1989-11-15 Production of thin-film transistor Pending JPH03157624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1296903A JPH03157624A (en) 1989-11-15 1989-11-15 Production of thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1296903A JPH03157624A (en) 1989-11-15 1989-11-15 Production of thin-film transistor

Publications (1)

Publication Number Publication Date
JPH03157624A true JPH03157624A (en) 1991-07-05

Family

ID=17839650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1296903A Pending JPH03157624A (en) 1989-11-15 1989-11-15 Production of thin-film transistor

Country Status (1)

Country Link
JP (1) JPH03157624A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993000603A1 (en) * 1991-06-28 1993-01-07 Dai Nippon Printing Co., Ltd. Black matrix base board and manufacturing method therefor, and liquid crystal display panel and manufacturing method therefor
US5477355A (en) * 1992-01-28 1995-12-19 Hitachi, Ltd. Process for producing the passivation layer of an active matrix substrate by back exposure
JPH0980476A (en) * 1995-09-12 1997-03-28 Nec Corp Active matrix substrate and manufacturing method thereof
JP2010134362A (en) * 2008-12-08 2010-06-17 Toppan Printing Co Ltd Thin film transistor array and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993000603A1 (en) * 1991-06-28 1993-01-07 Dai Nippon Printing Co., Ltd. Black matrix base board and manufacturing method therefor, and liquid crystal display panel and manufacturing method therefor
US5477355A (en) * 1992-01-28 1995-12-19 Hitachi, Ltd. Process for producing the passivation layer of an active matrix substrate by back exposure
JPH0980476A (en) * 1995-09-12 1997-03-28 Nec Corp Active matrix substrate and manufacturing method thereof
JP2010134362A (en) * 2008-12-08 2010-06-17 Toppan Printing Co Ltd Thin film transistor array and method for manufacturing the same

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