JPH0315825B2 - - Google Patents
Info
- Publication number
- JPH0315825B2 JPH0315825B2 JP60014729A JP1472985A JPH0315825B2 JP H0315825 B2 JPH0315825 B2 JP H0315825B2 JP 60014729 A JP60014729 A JP 60014729A JP 1472985 A JP1472985 A JP 1472985A JP H0315825 B2 JPH0315825 B2 JP H0315825B2
- Authority
- JP
- Japan
- Prior art keywords
- type impurity
- diffusion region
- gate electrode
- impurity diffusion
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/83138—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different shapes or dimensions of their gate conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/837—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising vertical IGFETs
- H10D84/839—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising vertical IGFETs comprising VDMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/8311—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different channel structures
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置に関するものであり、詳
しくは、同一チツプに高耐圧DMOS（diffused
MOS）と論理用CMOSとが混合形成された半導
体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device.
The present invention relates to a semiconductor device in which a MOS (MOS) and a logic CMOS are mixedly formed.
（従来の技術）
半導体集積回路の一種に、高耐圧DMOSと論
理用CMOSとが１チツプに一体形成されたもの
がある。(Prior Art) One type of semiconductor integrated circuit is one in which a high-voltage DMOS and a logic CMOS are integrally formed on one chip.
第３図は、従来のこのような装置の一例を示す
構成説明図であり、同一チツプVDMOS
（vertical DMOS）１とNMOS２およびPMOS
３が形成された例を示している。 FIG. 3 is a configuration explanatory diagram showing an example of such a conventional device, in which the same chip VDMOS
(vertical DMOS) 1, NMOS 2 and PMOS
3 is shown.
第４図は、このような装置の製造工程例の要部
説明図である。第４図ａにおいて、４はｐ型のシ
リコン基板であり、この基板４の表面にはｎ型不
純物の拡散領域５が形成された後にｎ型のエピタ
キシヤル層６が形成されている。このエピタキシ
ヤル層６には、基板４に達するようにしてｐ型不
純物の拡散領域７が形成されるとともに拡散領域
５に達するようにしてｎ型不純物の拡散領域８が
形成され、その後、表面の全面には酸化膜９が形
成されている。そして、この酸化膜９のNMOS
２が形成される部分には穴を開けてｐ型不純物の
拡散領域がｐウエル１０として形成され、その表
面には再度酸化膜が形成されている。第４図ｂに
おいて、酸化膜９のVDMOS１が形成される部分
に穴を開けてエピタキシヤル層６の表面近傍には
ｐ型不純物の拡散領域１１が形成され、さらにこ
の拡散領域１１にはｎ型不純物の拡散領域１２が
形成されている。そして、これらの表面にも再度
酸化膜が形成されている。第４図ｃにおいて、酸
化膜９のNMOS２およびPMOS３が形成される
部分に穴を開けてｐウエル１０にはｎ型不純物の
拡散領域１３が形成されるとともにエピタキシル
層６にはｐ型不純物の拡散領域１４が形成され、
これらの表面にも再度酸化膜が形成されている。
このようにしてエピタキシヤル層６に所定の拡散
領域を形成して各拡散領域の表面に酸化膜を形成
した後、酸化膜９の各ゲート電極に対応した所定
の位置に穴を開けてゲート酸化膜１５ａ〜１５ｃ
を形成し、さらに酸化膜９の各ソース電極および
ドレイン電極に対応した所定の位置に穴を開けて
これらゲート酸化膜１５および各拡散領域に金属
電極１６を設けることにより、第３図に示すよう
な半導体装置が実現できる。 FIG. 4 is an explanatory diagram of the main parts of an example of the manufacturing process of such a device. In FIG. 4a, 4 is a p-type silicon substrate, on the surface of which an n-type impurity diffusion region 5 is formed and then an n-type epitaxial layer 6 is formed. In this epitaxial layer 6, a p-type impurity diffusion region 7 is formed to reach the substrate 4, and an n-type impurity diffusion region 8 is formed to reach the diffusion region 5, and then the surface An oxide film 9 is formed on the entire surface. Then, the NMOS of this oxide film 9
A hole is made in the portion where the p-well 2 is to be formed, and a p-type impurity diffusion region is formed as a p-well 10, and an oxide film is again formed on the surface of the p-well 10. In FIG. 4b, a hole is made in the part of the oxide film 9 where the VDMOS 1 is formed, and a p-type impurity diffusion region 11 is formed near the surface of the epitaxial layer 6, and this diffusion region 11 also has an n-type impurity. An impurity diffusion region 12 is formed. Then, an oxide film is again formed on these surfaces. In FIG. 4c, holes are made in the portions of the oxide film 9 where NMOS2 and PMOS3 are formed, and an n-type impurity diffusion region 13 is formed in the p-well 10, and a p-type impurity is diffused in the epitaxial layer 6. A region 14 is formed;
An oxide film is again formed on these surfaces.
After forming predetermined diffusion regions in the epitaxial layer 6 in this way and forming an oxide film on the surface of each diffusion region, holes are formed in the oxide film 9 at predetermined positions corresponding to each gate electrode to perform gate oxidation. Membranes 15a to 15c
By forming holes in the oxide film 9 at predetermined positions corresponding to each source electrode and drain electrode and providing metal electrodes 16 in the gate oxide film 15 and each diffusion region, as shown in FIG. A semiconductor device can be realized.
（発明が解決しようとする問題点）
しかし、従来のこのような構造によれば、
NMOS２が形成されるエピタキシヤル層６の表
面近傍にはｐ型不純物の拡散領域がｐウエル１０
として比較的深く形成されていることから、この
ｐウエル１０の面積が比較的大きくなつて高密度
集積化の阻害要因となり、好ましくない。また、
ｐウエル１０を形成するための工程が増えるとと
もに、NMOS２をｐウエル１０を用いて構成し
ていることからVDMOS１、NMOS２および
PMOS３の閾値を合わせるための制御も必要に
なり、生産性にも問題がある。(Problem to be solved by the invention) However, according to this conventional structure,
Near the surface of the epitaxial layer 6 where the NMOS 2 is formed, a p-type impurity diffusion region is formed as a p-well 10.
Since the p-well 10 is formed relatively deeply, the area of the p-well 10 becomes relatively large, which becomes an impediment to high-density integration, which is not preferable. Also,
The number of steps required to form p-well 10 increases, and since NMOS2 is configured using p-well 10, VDMOS1, NMOS2 and
Control is also required to match the threshold value of PMOS3, which also poses a problem in productivity.
本発明は、このような点に着目したものであつ
て、その目的は、同一チツプに高耐圧DMOSと
論理用CMOSとが混合形成された半導体装置に
おいて、回路集積度および生産性を高めることに
ある。 The present invention focuses on these points, and its purpose is to increase the degree of circuit integration and productivity in a semiconductor device in which a high voltage DMOS and a logic CMOS are mixedly formed on the same chip. be.
（問題点を解決するための手段）
このような目的を達成する本発明は、同一チツ
プに高耐圧DMOSと論理用CMOSとが混合形成
された半導体装置において、
前記DMOSは、長さL1のゲート電極と、この
ゲート電極をマスクにして深さxjに拡散されるｐ
型不純物とを含み、これらゲート電極の長さL1
とｐ型不純物の深さxjはL1＞2xjの関係が成立す
るように設定され、
前記CMOSは、長さL2のゲート電極と、この
ゲート電極をマスクにして深さxjに拡散されるｐ
型不純物とを含み、これらゲート電極の長さL2
とｐ型不純物の深さxjはL2＜2xjの関係が成立す
るように設定されたことを特徴とする。(Means for Solving the Problems) The present invention achieves the above object, in a semiconductor device in which a high voltage DMOS and a logic CMOS are mixedly formed on the same chip, the DMOS has a length L1 . gate electrode and p diffused to depth xj using this gate electrode as a mask.
The length of these gate electrodes, including type impurities, is L 1
and the depth xj of the p-type impurity are set so that the relationship L 1 > 2xj holds, and the CMOS has a gate electrode with a length L 2 and is diffused to a depth xj using this gate electrode as a mask. p
The length of these gate electrodes, including type impurities, L 2
and the depth xj of the p-type impurity are set so that the relationship L 2 <2xj holds.
（実施例） 以下、図面を用いて詳細に説明する。(Example) Hereinafter, it will be explained in detail using the drawings.
第１図は本発明の一実施例を示す構成説明図、
第２図は第１図の装置の製造工程例の要部説明図
であり、第３図および第４図と同一部分には同一
符号を付けている。第２図ａは第４図ａとほぼ同
一の状態にある。第２図ｂにおいて、酸化膜９の
各素子１〜３に対応した部分に穴を開けて各素子
１〜３のゲート酸化膜１７ａ〜１７ｃを形成し、
さらにこれらゲート酸化膜１７ａ〜１７ｃの表面
の所定の位置には選択的に例えば多結晶シリコン
のような高融点導体よりなるゲート電極１８ａ〜
１８ｃを形成する。そして、ゲート電極１８ａを
マスクにしてVDMOS１が形成される部分のエピ
タキシヤル層６の表面近傍にイオン注入およびド
ライブ拡散によりｐ型不純物の拡散領域１９ａを
形成するとともに、ゲート電極１８ｂをマスクに
してNMOS２が形成される部分のエピタキシヤ
ル層６の表面近傍にイオン注入およびドライブ拡
散によりｐ型不純物の拡散領域１９ｂを形成す
る。ここで、VDMOS１のゲート電極１８ａの長
さをL1、NMOS２のゲート電極１８ｂの長さを
L2、ｐ型不純物の拡散領域１９ａ，１９ｂの拡
散の深さをxjとし、横方向にも深さ方向と同様に
拡散が行われるものとすると、これらの間には、
L1＞2xj、L2＜2xj
の関係が成立するように設定しておく。 FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention;
FIG. 2 is an explanatory view of the main parts of an example of the manufacturing process of the apparatus shown in FIG. 1, and the same parts as in FIGS. 3 and 4 are given the same reference numerals. FIG. 2a is in almost the same state as FIG. 4a. In FIG. 2b, holes are formed in portions of the oxide film 9 corresponding to the respective elements 1 to 3 to form gate oxide films 17a to 17c for each of the elements 1 to 3,
Furthermore, gate electrodes 18a to 18a made of a high melting point conductor such as polycrystalline silicon are selectively provided at predetermined positions on the surfaces of these gate oxide films 17a to 17c.
Form 18c. Then, using the gate electrode 18a as a mask, a p-type impurity diffusion region 19a is formed near the surface of the epitaxial layer 6 in the portion where the VDMOS 1 is formed by ion implantation and drive diffusion, and the NMOS 2 is formed using the gate electrode 18b as a mask. A p-type impurity diffusion region 19b is formed by ion implantation and drive diffusion in the vicinity of the surface of epitaxial layer 6 where the p-type impurity is formed. Here, the length of the gate electrode 18a of VDMOS1 is L1 , and the length of the gate electrode 18b of NMOS2 is L1.
L 2 , the diffusion depth of the p-type impurity diffusion regions 19a and 19b is xj, and assuming that diffusion is performed in the lateral direction as well as in the depth direction, between these, L 1 >2xj, Set so that the relationship L 2 < 2xj holds.
その後、第２図ｃに示すように、VDMOS１の
ソースのためにｐ型不純物の拡散領域１９ａの表
面近傍にイオン注入およびドライブ拡散によりｎ
型不純物の拡散領域２０ａを形成し、NMOS２
のソースおよびドレインのためにｐ型不純物の拡
散領域１９ｂの表面近傍にイオン注入およびドラ
イブ拡散によりｎ型不純物の拡散領域２０ｂを形
成し、PMOS２のソースおよびドレインのため
にエピタキシヤル層６の表面近傍にイオン注入お
よびドライブ拡散によりｐ型不純物の拡散領域２
１を形成する。このようにしてエピタキシヤル層
６に所定の拡散領域を形成した後、酸化膜９の各
ソース電極およびドレイン電極に対応した所定の
位置に穴を開けて各拡散領域に導体２２ａ〜２２
ｆを設けることにより、第１図に示すような半導
体装置が実現できる。ここで、導体２２ａは
VDMOS１のソース電極となり、導体２２ｂは
VDMOS１のドレイン電極となり、導体２２ｃ，
２２ｄはNMOS２のソース、ドレイン電極とな
り、導体２２ｅ，２２ｆはPMOS３のソース、
ドレイン電極となる。 Thereafter, as shown in FIG. 2c, ion implantation and drive diffusion are performed near the surface of the p-type impurity diffusion region 19a for the source of VDMOS1.
A type impurity diffusion region 20a is formed, and the NMOS2
An n-type impurity diffusion region 20b is formed near the surface of the p-type impurity diffusion region 19b for the source and drain of the PMOS 2 by ion implantation and drive diffusion, and an n-type impurity diffusion region 20b is formed near the surface of the epitaxial layer 6 for the source and drain of the PMOS 2. P-type impurity diffusion region 2 is formed by ion implantation and drive diffusion into
Form 1. After forming the predetermined diffusion regions in the epitaxial layer 6 in this way, holes are made in the oxide film 9 at predetermined positions corresponding to each source electrode and drain electrode, and conductors 22a to 22 are formed in each diffusion region.
By providing f, a semiconductor device as shown in FIG. 1 can be realized. Here, the conductor 22a is
The conductor 22b becomes the source electrode of VDMOS1.
It becomes the drain electrode of VDMOS1, and the conductor 22c,
22d becomes the source and drain electrodes of NMOS2, and conductors 22e and 22f become the source and drain electrodes of PMOS3.
It becomes the drain electrode.
このような構成において、NMOS２を形成す
るｐ型不純物の拡散領域２１ｂはゲート電極１８
ｂの下部で接続されていることから、従来のｐウ
エルと同様の機能を持つことになり、従来必要で
あつたｐウエルの拡散工程を省略することができ
るとともにｐウエルの面積の大きさに起因する高
密度集積化の阻害要因もなくなつてより集積度を
高めることができる。そして、VDMOS１および
NMOS２に着目すると、これらはほぼ等しい拡
散深さを有するｐ型不純物の拡散領域１９ａ，１
９ｂにほぼ等しい拡散深さを有するｎ型不純物の
拡散領域２０ａ，２０ｂが形成されていることか
らほぼ等しい閾値となり、製造工程における制御
パラメータを１つ減らせることから生産管理が容
易になる。 In such a configuration, the p-type impurity diffusion region 21b forming the NMOS 2 is connected to the gate electrode 18.
Since the connection is made at the bottom of the p-well, it has the same function as a conventional p-well, making it possible to omit the conventional p-well diffusion process and reducing the area of the p-well. This eliminates the impediments to high-density integration, and the degree of integration can be further increased. And VDMOS1 and
Focusing on NMOS2, these are p-type impurity diffusion regions 19a and 1 having approximately equal diffusion depths.
Since the n-type impurity diffusion regions 20a and 20b are formed with a diffusion depth approximately equal to 9b, the threshold values are approximately equal, and the number of control parameters in the manufacturing process can be reduced by one, making production management easier.
（発明の効果）
以上説明したように、本発明によれば、同一チ
ツプに高耐圧DMOSと論理用CMOSとが混合形
成された半導体装置において、回路集積度および
生産性を高めることができる。(Effects of the Invention) As described above, according to the present invention, it is possible to increase the degree of circuit integration and productivity in a semiconductor device in which a high voltage DMOS and a logic CMOS are mixedly formed on the same chip.
第１図は本発明の一実施例を示す構成説明図、
第２図はその製造工程例の要部説明図、第３図は
従来の装置の一例を示す構成説明図、第４図はこ
のような装置の製造工程例の要部説明図である。
１……VDMOS、２……NMOS、３……
PMOS、４……ｐ型シリコン基板、５，８，２
０……ｎ型不純物拡散領域、６……ｎ型エピタキ
シヤル層、７，１９，２１……ｐ型不純物拡散領
域、９……酸化膜、１７……ゲート酸化膜、１８
……ゲート電極、２２……導体。
FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention;
FIG. 2 is an explanatory view of the main part of an example of the manufacturing process, FIG. 3 is an explanatory diagram of the configuration of an example of a conventional device, and FIG. 4 is an explanatory diagram of the main part of an example of the manufacturing process of such a device. 1...VDMOS, 2...NMOS, 3...
PMOS, 4...p-type silicon substrate, 5, 8, 2
0...n-type impurity diffusion region, 6...n-type epitaxial layer, 7, 19, 21...p-type impurity diffusion region, 9...oxide film, 17...gate oxide film, 18
...Gate electrode, 22...Conductor.
Claims (1)
とが混合形成された半導体装置において、 前記DMOSは、長さL1のゲート電極と、この
ゲート電極をマスクにして深さxjに拡散されるｐ
型不純物とを含み、これらゲート電極の長さL1
とｐ型不純物の深さxjはL1＞2xjの関係が成立す
るように設定され、 前記CMOSは、長さL2のゲート電極と、この
ゲート電極をマスクにして深さxjに拡散されるｐ
型不純物とを含み、これらゲート電極の長さL2
とｐ型不純物の深さxjはL2＜2xjの関係が成立す
るように設定されたことを特徴とする半導体装
置。[Claims] 1 High voltage DMOS and logic CMOS on the same chip
In the semiconductor device, the DMOS includes a gate electrode having a length L1 , and a p-type transistor diffused to a depth xj using this gate electrode as a mask.
The length of these gate electrodes, including type impurities, is L 1
and the depth xj of the p-type impurity are set so that the relationship L 1 > 2xj holds, and the CMOS has a gate electrode with a length L 2 and is diffused to a depth xj using this gate electrode as a mask. p
The length of these gate electrodes, including type impurities, L 2
A semiconductor device characterized in that the depth xj of the p-type impurity is set such that the relationship L 2 <2xj holds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60014729A JPS61174666A (en) | 1985-01-29 | 1985-01-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60014729A JPS61174666A (en) | 1985-01-29 | 1985-01-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61174666A JPS61174666A (en) | 1986-08-06 |
| JPH0315825B2 true JPH0315825B2 (en) | 1991-03-04 |
Family
ID=11869216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60014729A Granted JPS61174666A (en) | 1985-01-29 | 1985-01-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174666A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2721155B2 (en) * | 1987-02-19 | 1998-03-04 | 株式会社東芝 | Semiconductor device |
| JPH0783092B2 (en) * | 1987-06-24 | 1995-09-06 | 日本電気株式会社 | Semiconductor device |
| JPH01108761A (en) * | 1987-10-21 | 1989-04-26 | Sharp Corp | High breakdown strength semiconductor device |
| JPH03178161A (en) * | 1989-12-06 | 1991-08-02 | Mitsubishi Electric Corp | Mos semiconductor integrated circuit |
| JPH04239178A (en) * | 1991-01-11 | 1992-08-27 | Nec Corp | Integrated circuit |
| JP2746175B2 (en) * | 1995-02-28 | 1998-04-28 | 日本電気株式会社 | High voltage semiconductor device |
-
1985
- 1985-01-29 JP JP60014729A patent/JPS61174666A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61174666A (en) | 1986-08-06 |
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