JPH0315954A - Access system for two-dimensional information memory - Google Patents

Abstract

PURPOSE:To attain a high speed processing and to eliminate overhead in a memory input/output processing by directly accessing a real memory in virtual memory space allocated to space to be processed. CONSTITUTION:A virtual memory address (X,Y) from an information processor 1 is converted into a real address in an address conversion part 2, and the real memory is directly accessed in virtual memory 3 space where the information processor 1 executes the processing by the shift rotary processing of a transfer data byte with the memory, byte division and byte synthesis. Consequently, the real memory can be directly accessed in virtual memory space 3 which is allocated to space to be processed for the information processor 1 which is to execute the processing of two-dimensional information. Thus, the overhead of the memory access processing can be eliminated.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 7) Means for solving the problem to be solved by the invention (Figure 1) Effect (Figure 1) Implementation Examples (Figures 2 to 6) Effects of the invention [Summary] Regarding the access method of two-dimensional information memory, it is possible to directly access real memory in a virtual memory space in which information processing equipment executes processing, The aim is to eliminate the overhead of access processing and enable high-speed processing.In the access method of two-dimensional information memory when writing and reading two-dimensional information in 1-byte units to real memory. , an address converter that converts a virtual memory address to a real address based on preset parameters, a real address raw base that reads the next real address from the converted real address, and information in 1-byte units. A two-dimensional An information processing device that attempts to process information is configured to be able to directly access real memory in a virtual memory space allocated to a space to be processed.

[Industrial application field]

The present invention relates to an access method for two-dimensional information memory, and more specifically, it is used when processing two-dimensional information such as image data. This paper relates to a method for accessing two-dimensional information memory.

[Conventional technology]

FIG. 7 is an explanatory diagram of a memory access method in a conventional information processing device.

In the figure, 50 is an information processing unit (CPU), 51 is a human output processing unit, 52 is a memory, 53 is a memory address generation unit, 54 is an input/output data pit processing unit, and 55 is a memory access unit.

Conventionally, when processing two-dimensional information such as images, it has been difficult to transfer information from the information processing equipment to the real memory due to restrictions on the address assignment of the memory chip that stores the information and the data format transferred between the two-dimensional information input/output device. When accessing, memory access processing was performed.

As illustrated, in the information processing unit (CPU) 50,
Each process is executed as in (a), (b), and (c), and at that time, memory access is made to the memory 52. Memory access at this time is performed as follows.

First, from the information processing unit (CPU) 50 to the input/output processing unit 51
Sends a virtual address to. This virtual address is converted into a real address in the memory address generation unit 53.

The real address converted as described above is subjected to data bit processing such as bit position movement across multiple bytes in the input/output data pit processing section 54.

Thereafter, the memory access unit 55 accesses the memory 52. In this way, when accessing the real memory 52, it is necessary to execute various processes in the input/output processing section 5l. [Problems to be solved by the invention] The conventional devices described above had the following drawbacks. In other words, when accessing real memory from information processing equipment,
Since it requires memory access processing, it creates overhead and makes it difficult to achieve high-speed processing. The present invention eliminates these conventional drawbacks and enables information processing equipment to directly access real memory in the virtual memory space in which it executes processing, eliminating the overhead of memory access processing and enabling high-speed processing. The purpose is to do so.

[Means to solve the problem]

In order to achieve the above object, the present invention is as follows.

FIG. 1 is a principle diagram of an access method of a two-dimensional information memory according to the present invention.

In the figure, 1 is an information processing device (for example, a CPU), 2
is the address conversion unit, 3 is the virtual memory space, 4 is the real memory (real memory space), 5 is the real address raw bottom, and 6 is the shift processing unit. The address conversion unit 2 has a virtual memory address (X
, Y) to a real memory address is set in advance from the information processing device 1.

The real memory 4 is connected to the real memory 4 from the information processing device l.
When accessing byte units, the memory byte information (data) is divided into the upper bit side and the lower bit side at arbitrary bit positions, and the structure is such that two consecutive memory addresses can be assigned to the upper and lower sides at the same time. I'll be strong.

The real address generation unit 5 converts the address (Z) of the real memory 4 converted by the address conversion unit 2 and the focus position address (
ΔZ) is input, and the address (Z) is incremented by 1 to generate the next address (Z+1). In the shift processing section 6, the bit operation amount information (ΔZ) is manually input, and based on this information (ΔZ), the information processing device 1
The data transferred between the memory and the memory is shifted and rotated and transferred to the real memory 4. [Function] Since the present invention is configured as described above, it has the following functions. In other words, the virtual memory address (XSY
) into a real address in the address conversion unit 2, and then performs shift rotation processing of transfer data bytes to and from the memory, byte division, and byte composition to create a virtual memory on which the information processing device 1 executes processing. In space, real memory is directly accessed.

As shown in the figure, virtual memory address (X, Y) corresponds to real addresses (Z) and (Z+1) in real memory space 4, and address (Z) - is shifted from the position shifted by (ΔZ). The data on the upper bit side is entered, and the data on the lower bit side is (
Enter Z+1). In this way, an information processing device attempting to process two-dimensional information can directly access real memory in the virtual memory space allocated to the space to be processed.

This makes it possible to eliminate the overhead of memory access processing.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. FIG. 2 is an overall configuration diagram of one embodiment of the present invention.

In the figure, l is an information processing device, 2 is an address translation unit,
4 is a real memory (real memory space), 5 is a real address raw bottom part, 6-1 and 6-2 are a write barrel shifter and a read barrel shifter, respectively, which constitute a shift processing section.
7 is an adder (+1 addition), 8 is a selector, and 9 is an address selection control section. A virtual address (X, Y) output from an information processing device (for example, a CPU) 1 is input to an address conversion section 2. The address conversion unit 2 has an address conversion table for converting virtual addresses to real addresses, and this address conversion table contains various parameters etc. for address conversion from the information processing device 1 in advance. Set it. When memory access is performed using the above virtual address (X, Y), address translation is performed using the address translation table of the address translation unit 2, and the real address (Z) is
, the bit operation amount information (△Z) is generated. The real address (Z) is inputted to the real address reading unit 5, inputted to one input terminal of the selector 8, and inputted to the adder 7 where +1 is added. input to the other human power terminal. Bit operation amount information (ΔZ
) is input to the address selection control unit 9, the write barrel shifter 6-1, and the read barrel shifter 6-2, and performs bit position manipulation. In the address selection control section 9, the bit operation amount information I! A control signal is generated based on (Δ2) and output to the selector 8. The selector 8 performs a manual signal selection operation based on the control signal, outputs either the real address (Z) or (Z+1),
Send to real memory 4. Read data and write data sent and received between the information processing device 1 and the real memory 4 are handled in byte units. The write data (write data) sent from the information processing device 1 is shifted to the right by the value of (Δ2) mentioned above by the write barrel shifter 6-1, and the data spilled from the right end is returned to the left end. Furthermore, after the read data (read data) from the real memory 4 is input to the read barrel shifter 6-2, it is shifted to the left by the value of (ΔZ),
The spilled portion is returned to the right edge. When writing data from the writing barrel shifter 671 to the real memory 4, the real address (Z) and (Z+
1) are stored separately. FIG. 3 is an explanatory diagram of the correspondence between virtual memory and real memory in the above embodiment. Input/output devices for two-dimensional information such as images are interfaced by serial transfer using Rusk Scan etc.
Each byte of information is matched in both virtual memory and real memory. In virtual memory space 3, one byte of information specified by two-dimensional coordinates (X, Y) is divided into the byte at address Z excluding the left ΔZ bit and the ΔZ bit at address Z+1 in real memory space 4. Correspondence can be arranged. That is, the real memory is accessed by the virtual address (X, Y) from the information processing device 1 explained in FIG.
xSy), when accessing the real memory by (X,
It is necessary to calculate (Z) and (ΔZ) from Y) and perform bit operations using (ΔZ) on the information at addresses (Z) and (2+1) in real memory. FIG. 4 is an explanatory diagram of address conversion in the above embodiment. The address (Z) necessary for real memory access from the virtual address (X, Y) and the bit operation amount information (ΔZ) are
It is generated using the translation table of the address translation unit 2 shown in the figure.

In this example, (ΔZ) is 3 (lower 3 bits).
Moreover, (Z) is calculated by the formula Z=K-Y+J as shown in the figure. In other words, (Z) is the value obtained by multiplying Y by K, the number of bytes in one line, and
This is the value obtained by adding the byte number J (the value excluding the lower three digits of X).

FIG. 5 is an explanatory diagram of address selection control in the above embodiment, (A) is an explanatory diagram of the address selection control section, (B
) indicates a logical table.

For example, the structure is as shown in FIG. 5(A), and appropriate address switching is performed by the above-mentioned ΔZ.

As shown in the logic table in (B), for example, Δz=0
Then the control signal (CNTO-CNT7) is rl 1 1
1 1 1 1 1J, and if ΔZ=1, r01
111111”, if ΔZ=2, “00111ll1”
, if ΔZ=3, then r00011111''. This M control signal (CNTO to CNT7) is sent to the selector 8 shown in FIG. 2, and the real address (Z) and (Z+1) are
A selection is made, and one of the real addresses is sent to the real memory 4.

FIG. 6 is an explanatory diagram of the shift and rotation processing in the above embodiment, and (A) is an explanatory diagram of the human output data pattern;
(B) shows the correspondence diagram with virtual memory. The input data to the writing barrel shifter 6-1 is 1 byte (Bo = 8 bits of Bt) as shown in (A), and this data (A) is input to the writing barrel shifter 6-1.
is shifted by 3 bits (ΔZ=3). At this time, the data is shifted to the right, and the data B5, B6, and B that spilled from the right end are rotated and returned to the left end, (
Memory input pattern (BsBsBtBoB) shown in
tB2BsB4) is input to real memory 4. In the real memory 4, according to the logic table in FIG.
Further, "rBS-Bt" shown in (2) is stored in (Z+1) at the same time. To read the data stored in the real memory 4 in this way, proceed as follows. The data stored in the real addresses (Z) and (Z+1) are read out at the same time according to the logic table shown in FIG. is output to . The reading barrel shifter 6-2 shifts 3 bits (ΔZ=3) to the left,
Rotate to get output data (to). This state is shown in figure (B) and data is obtained. This situation is shown in figure (B). As a result, the read data (f) becomes the same as the data shown in (a), and is sent to the information processing device 1. Note that the present invention is not limited to the above embodiments, but can also be implemented as follows. (1) In the above embodiment, the table conversion method is used for address conversion, and the table contents are preloaded from the information processing equipment to provide flexibility in allocating virtual memory addresses to the memory space to be processed. .

In this case, the address of K shown in FIGS. 3 and 4 may be converted using a sum-of-products circuit based on register settings from the information processing device.

(2) In the above information, bit operation amount information (△Z)
We have explained an example in which the address translation unit 2 uses
This (ΔZ) may be used in an information processing device, for example, a CPU, and may be supplied to each part. [Effects of the Invention] As explained above, the present invention has the following effects.

(1) In information processing equipment, real memory can be accessed using virtual memory addresses allocated in a two-dimensional space to be processed, without being aware of the address structure of real memory. (2) Since conversion from virtual addresses to real addresses, shifts, rotations, etc. during data transfer can be processed by hardware, high-speed processing is possible and overhead in memory input/output processing is eliminated.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of an access method of a two-dimensional information memory according to the present invention, Fig. 2 is an overall configuration diagram of an embodiment of the present invention, and Fig. 3 is a correspondence between virtual memory and real memory in the above embodiment. FIG. 4 is an explanatory diagram of address conversion in the above embodiment. FIG. 5 is an explanatory diagram of address selection control in the above embodiment. FIG. 6 is an explanatory diagram of shift processing in the above embodiment. The figure is an explanatory diagram of the conventional memory access method. 1 - Information processing equipment 2 - Address conversion section 3 - Virtual memory space 4 - Real memory space 5 - Real address generation section 6 --- Shift processing section

Claims (1)

[Claims] When writing or reading two-dimensional information such as image data into or from the real memory (4) in 1-byte units,
In the two-dimensional information memory access method performed from the information processing device (1) to the real memory (4), the virtual memory address (
an address conversion unit (2) that converts the address (X, Y) into a real address (Z) based on preset parameters, etc.;
A real address generation unit (5) that generates Z+1) divides the above-mentioned 1-byte information into upper bits and lower bits at arbitrary bit positions, and concatenates the upper bits and lower bits at the same time. A real memory (4) to which two memory addresses can be assigned, and a shift processing unit that shifts and rotates information (data) transferred between the real memory (4) and the information processing device (1) by an arbitrary number of bits. (6)
information processing equipment (1) that attempts to process two-dimensional information.
), an access method for a two-dimensional information memory is characterized in that the real memory (4) can be directly accessed in the virtual memory space (3) allocated to the space to be processed.