JPH0316087A - Static type semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten the access time by equalizing separately a group containing each pair of a first plural pieces of complementary data line pairs or a pair of a second plural pieces being smaller than the first plural pieces. CONSTITUTION:This device is provided with a memory cell array divided into blocks BL containing the first plural pieces of complementary data line pairs l, and an equalizing means 30 for equalizing separately a group C containing each pair of the first plural pieces of complementary data line pairs l or a pair of the second plural pieces being smaller than the first plural pieces in each block BL. That is, in each of the memory cell arrays divided into the blocks BL, the first plural pieces of complementary data line pairs l contained therein are equalized separately at every pair or at every the second plural pairs. In such a way, the access time is shortened, and it does not occur that the access time becomes long due to an increase of the number of memory cells.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a static semiconductor memory device, and in particular,
The present invention relates to a static semiconductor memory device divided into blocks.

[Prior Art] Semiconductor storage devices are broadly classified into SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) depending on their storage method.

SRAM is a static semiconductor memory device whose stored data does not disappear unless the power is turned off, but DRA
In M, the stored data gradually disappears over time if left alone even when power is applied.

FIG. 5 is a schematic block diagram showing the general configuration of a conventional one-chip SRAM. Referring to Figure 5, this SR
AM includes a memory cell matrix section 1 including a memory cell array in which memory cells for storing data are arranged in a matrix, and a memory cell at which position (address) in the memory cell array included in the memory cell matrix section 1. A row address input terminal 2 and a column address input terminal 3 each receiving a row address signal and a column address signal for selecting whether to read or write data, and a row address input terminal! A row address buffer 4 for amplifying or inverting a row address signal applied to
and a column address buffer 5 for amplifying or inverting a column address signal applied to the column address input terminal 3.

This SRAM further includes a row decoder 6 that decodes and decodes the row address signal taken in by the row address buffer 4, and a column decoder 6 that decodes and decodes the column address signal taken in by the row address buffer 5. A decoder 7, a multiplexer 8 that writes and reads data to and from a memory cell selected by a row address signal and a column address signal, a sense amplifier that senses and amplifies the small amplitude signal voltage read out by the multiplexer 8, and a sense amplifier that senses and amplifies the small amplitude signal voltage read out by the multiplexer 8. an output buffer 10 for further amplifying the signal amplified by 9 in order to take it out to the outside; a data output terminal 11 for receiving the output of the output buffer 10 as final continuous data; It includes a data input terminal 12 that receives an input signal (write data), and a data buffer 13 that amplifies the input signal applied to the data input terminal 12 and supplies it to the multiplexer 8 . This SRAM further has
A chip selector input terminal 14 receives a chip selector signal indicating whether this chip is in a selected state or a non-selected state, and determines whether data is to be read or written to a memory cell in the memory cell matrix section 1. A read/write control input terminal 15 receives a read/write control signal for specifying a chip selector signal applied to the chip selector manual terminal 14 and a read/write control signal applied to the read/write control input terminal 15. In response to the control signal,
When this SRAM chip is in the selected state, the read/write control signal controls the sense amplifier 9, output buffer 10, human buffer 13, etc. to set this SRAM in the read state or write state in accordance with the read/write control signal.
The write control circuit 16 detects a change in the row address signal taken in by the row address buffer 4 and the column address signal taken in by the column address buffer 5, and the memory cell matrix section 1, row decoder 6, sense Provides various internal synchronization signals for controlling the amplifier 9, output buffer 10, etc. ATD (Addres)
s Transition Detector) circuit 17.

SRAM basically does not require a synchronization circuit that generates synchronization signals, but in order to achieve even higher performance, this SRAM
In M, a synchronous circuit called the ATD circuit 17 as described above is introduced as a part of the peripheral circuit.

FIG. 6 shows the specific internal configuration of the memory cell matrix section 1 and its peripheral parts of the SRAM shown in FIG. 5. For simplicity, FIG. FIG. 2 is a schematic block diagram showing a case where a matrix structure is formed.

Referring to FIG. 6, memory cells 24a, 24b, 24C
, and 24d are arranged in a matrix of 2 rows and 2 columns,
Two memory cells 24a and 24b arranged in each row
and 24c and 24d are commonly connected to hole word lines 22 and 23 connected to the row decoder 6, respectively, and the two memory cells 24a and 24c arranged in the same column form a complementary data line pair for propagating complementary data. Two bit lines 20a and 20b forming a bit line pair
Similarly, memory cells 24b and 24d
Two bit lines 21 forming another bit line pair
Provided between a and 2lb. Bit line 20a, 2
An N-channel MOS transistor 2 for bit line load is connected between each of 0b, 21a, and 21b and the power supply 18.
5 a, 2 5 b, 26 a. and 26b are provided, respectively. This allows each bit line to
The threshold voltage of the bit line load transistor is subtracted from the potential of the bit line load transistor. A P-channel MOS} transistor 30a is provided between the bit lines 20a and 20b constituting one bit line pair as a bit line equalizer for short-circuiting them, and similarly a bit line 21a constituting the other bit line pair is provided. A P-channel MOS transistor 30b is provided between and 2lb. The equalization control signal human power terminal 31 and the equalizers 30a and 30b receive an equalization control signal for controlling ON/OFF of the bit line equalizers 30a and 30b provided in each column (column) in this way.
An inverter 32 is connected between the gate and the gate as an equalization buffer for buffering the equalization control signal.
is provided. Two bit lines 2 forming a bit line pair
0a and 20b are input/output lines (hereinafter referred to as 1/O lines) 29a that are responsible for transmitting read data from the memory cell to the sense amplifier 9 and transmitting write data from the input buffer 13 to the memory cell. and 29b via N-channel MOS transistors 27a and 27b, respectively. Similarly, two bit lines 21a and 21b constituting another bit line pair are connected to I/O via N channel MOS transistors 28a and 28b.
Connected to O lines 29a and 29b, respectively. Gates of transistors 27a and 27b and transistor 28
The gates of a and 28b are connected to different signal lines connected to column decoder 7, respectively. transistor 27
a, 27b, 28a, and 28b and I/O line 2
9a and 29b are the multiplexer 8 in FIG.
, and the transistor 2 7 a. 2 7 b
, 28 a+ and 28b play the role of transfer gates. During data writing and data reading, signals from column decoder 7 are used to connect transfer gates (
Transistors 27a and 27b or transistors 28a and 28b) become conductive. As a result, a complementary level voltage corresponding to the human input signal applied to the data input terminal 12 when data is continuously output is applied to the bit line pair corresponding to the selected memory cell via the I/O lines 29a and 29b. be done.

When data is successively generated, voltages at complementary levels corresponding to the data stored in the selected memory cell are applied to the bit line pair corresponding to the selected memory cell. The voltage on this bit line pair is set to I by the conducting transfer gate.
It is applied to the sense amplifier 9 via /O lines 29a and 29b.

FIGS. 7(a) and 7(b) show each memory cell 24a, 2
4b, 24c, and 24d are circuit diagrams showing examples of general internal configurations.

FIG. 7(a) shows a high resistance load type NMOS memory cell. Referring to FIG. 7(a), this memory cell includes a driver transistor (N-channel MOS transistor) 4
1a and 4lb, access transistors (N-channel MOS} transistors) 42a and 42b, and load resistors 43a and 43b. In this memory cell, a driver transistor 41a and a load resistor 43a are connected in series, and a driver transistor 4l
A series connection of the load resistor 43b and the load resistor 43b is provided between the power supply 18 and one ground. Access transistor 42a
is provided between one bit line b1 of two bit lines b1 and b2 constituting a bit line pair and a storage node 45a which is a connection point between a driver transistor 41a and a load resistor 43a. Similarly, access transistor 42b is provided between the other bit line b2 and storage node 45b, which is the connection point between driver transistor 4lb and load resistor 43b.

The gates of access transistors 42a and 42b are both commonly connected to one word line W, the gate of driver transistor 41a is connected to storage node 45b,
The gate of driver transistor 41b is connected to storage node 45
Connected to H. When this memory cell is in a selected state during data writing and data reading, a high level voltage is applied to the word line W, so the access transistor 42
a and 42b are brought into conduction. As a result, the voltage level of bit line b1 can be transmitted to storage node 45a, and the voltage level of bit line b2 can be transmitted to storage node 45b. When writing data, bit lines b1 and b
2, a voltage of a complementary level corresponding to the data to be written is applied.

Therefore, voltages at complementary levels are applied to nodes 45a and 45b. For example, bit line b
When a high level voltage is applied to node 45
a becomes high level. Thereafter, when the voltage applied to the word line W switches to low level and this memory cell becomes unselected, access transistors 42a and 4
2b are both non-conductive. This allows bit line b
1 and b2 voltage levels can no longer be transmitted to nodes 45a and 45b. On the other hand, at this time, the transistor 4lb becomes conductive due to the high level voltage previously applied to the node 45a, and the transistor 41a becomes conductive due to the low level voltage applied to the node 45b.
is non-conducting.

Therefore, no current flows through the resistor 43a, and the voltage level at the node 45a is held at a high level, whereas current flows from the power supply 18 through the resistor 43b, and the voltage level at the node 45b becomes the voltage level at the ground 19, that is, at a low level. Retained. In this way, when writing data, the voltage level applied to bit lines b1 and b2 (i.e., manual data)
is held (stored) in nodes 45a and 45b.

When data continues, this memory cell becomes selected and a high-level voltage is applied to the word line W, transistors 42a and 42b become conductive, and as a result, the voltage level held at the node 45a is transferred to the bit line b1. The voltage level held at node 45b is transmitted to line b2.

FIG. 7(b) shows a CMOS type memory cell.

Referring to FIG. 7(b), this memory cell is shown in FIG.
Load resistors 43a and 43b in the high resistance load type NMOS memory cell shown in a) are replaced with P channel MOS transistors 44a and 44b, respectively. The gates of transistors 41a and 44a are commonly connected to node 45b, and the gates of transistors 41b and 44b are connected to node 45b.
5a in common. Therefore, at the end of data writing, transistors 41a and 44a invert the voltage level of node 45b and apply it to node 45a, thereby fixing the voltage level of node 45a to the level applied by bit line b1 at the time of data writing. However, transistors 41b and 44b invert the voltage level of node 45a and apply it to node 45b, thereby fixing the voltage level of node 45b to the level applied by bit line b2 during data writing.

Next, the operations of the SRAM configured as described above during data reading and data writing will be described. For explanation, please refer to Figures 5 and 6. 8 in addition to FIG. 7. FIG. 8 is a timing diagram showing the waveforms of internal signals generated in the SRAM having the above configuration when reading data.

First, the operation of the SRAM when such a sequence occurs will be explained.

Now, the row address signal and column address signal for selecting the memory cell 24c in FIG.
(see FIG. 5) and column address input terminal 3 (see FIG. 5), respectively. In this case, referring to FIG. 6, row decoder 6 applies a high level voltage only to word line 23, and column decoder 7 applies a high level voltage to the gates of transistors 27a and 27b to make them conductive. is being applied.

As a result, the access transistors in the memory cell 24c (the access transistors 42a and 42b in FIG. 7(a) or 7(b)) are conductive, and the two storage nodes (in the memory cell 24c) are connected to the bit lines 20a and 20b. The voltage levels (data) of storage nodes 45a and 45b in FIG. 7(a) or 7(b) are respectively transmitted. Furthermore, since transistors 27a and 27b are conductive, the voltage level of bit line 20a is transmitted to I/O line 29a, and the voltage level of bit line 20b is transmitted to 1/0 line 29b. In other words, the memory cell 24c is connected to the I/O line pair 29a and 29b.
The data stored in has been retrieved. At this time,
The chip selector input terminal 14 in FIG.
A signal that selects the RAM chip is given to the read/write control manual terminal 15, and a signal that designates the read state is given to the read/write control manual terminal 15. Therefore, the sense amplifier 9 is controlled by the read/write control circuit 16 and the I/O lines 29a and 29
The voltages at two complementary levels corresponding to the data stored in the memory cell 24c, which are taken out in the memory cell 24c, are differentially amplified. The resulting signal is further amplified under the control of output buffer 10 or read/write control circuit 16, and is applied to data output terminal 11 as final read data.

Next, assume that data is subsequently read from the memory cell 24a from such a state. In addition,
In the description, it is assumed that reading data from memory cell 24C causes the voltage levels of bit lines 20a and 20b to become high and low levels, respectively, and that the data stored in memory cell 24a is opposite to that in memory cell 24c.

In such a case, referring to FIG. 5, the row address signal and column address signal applied to the row address input terminal 2 and column address input terminal 3 change from selecting memory cell 24c to selecting memory cell 24a. do. Accordingly, the address signals output from row address buffer 4 and column address buffer 5 change as shown in FIG. 8(a). Next, the ATD circuit 17 detects this change in the address signal and generates a one-shot pulse having a predetermined pulse width as shown in FIG. 8(b). This one-shot pulse is applied to the equalize control signal input terminal 31 in FIG. 6 as a bit line equalize control signal. Therefore, the equalize control signal is inverted and amplified by the equalize buffer 32, and the equalizer 30a is a P-channel MOS transistor.
and 30b. That is, a low level one-shot pulse is applied to the gates of equalizers 30'a and 30b, and equalizers 30'a and 30'
b becomes conductive. As a result, the two bit lines 20a and 20b, and 21a and 21b constituting each bit line pair are short-circuited and have the same potential.

That is, as shown in FIG. 8(C), bit line 2
With the generation of a one-shot pulse from the ATD circuit 17, the voltage on the bit line 20a drops from the high level voltage applied when reading data from the memory cell 24c.
The voltage of b increases from the low level voltage applied when data is successively output from memory cell 24c, and as a result, these voltages become equal to each other. Therefore, bit line 20a
The voltage of 20b and 20b becomes an intermediate potential that is neither high level nor low level during period t corresponding to the period in which the one-shot pulse is output from the ATD circuit 17. At this time, memory cell 24C is still in the selected state and transistors 27a and 27b remain conductive. Therefore, such bit line equalization (
With the potential equalization), the outputs of I/O lines 29a and 29b and sense amplifier 9 are also equalized. At the same time, A.T.
Based on the one-shot pulse from the D circuit 17, the row decoder 6 outputs the word line 22 after equalization as described above.
The voltage level of word line 23 is switched to high level, and the voltage level of word line 23 is switched to high level. Column decoder 7 selects memory cell 24a and continues to apply voltage to the gates of transistors 27a and 27b to make them conductive.

Therefore, as shown in FIG. 8(d), the voltage of the word line 22 changes from the low level to the high level when data continues to be output from the memory cell 24c, and conversely, the voltage of the word line 23 changes from low level to high level. , Figure 8(e)
As shown in FIG. 3, the level changes from the high level to the low level when data is read from the memory cell 24c.

As a result, the memory cell 24a is placed in the selected state instead of the memory cell 24c, and the two access transistors in the memory cell 24a are rendered conductive.

Here, the data stored in the memory cell 24a is stored in the memory cell 2
It is complementary to that of 4c. Therefore, bit lines b1 and b2 in FIG. 7 correspond to bit line 2 in FIG.
0a and 20b, respectively, and when the word line W in FIG. 7 corresponds to the word line 22 in FIG. 6, with reference to FIGS. and 45b are at low level, and 45b is at high level, respectively, and driver transistors 41a and 41b are in a conductive state and a non-conductive state. Since word line 22 is now selected at a high level, both access transistors 42a and 42b in memory cell 24a are conductive.

Therefore, the equalize control signal becomes low level,
When equalizers 30a and 30b become non-conductive, power supply 18 - bit line load transistor 25a - bit line 2
A direct current flows through the path 0a-access transistor 42a-driver transistor 41a-ground 19. However, the other path, i1iij18, bit line load transistor 25b - bit line 20b - access transistor 42b - driver transistor 41
A driver transistor 4lb is connected to the b-ground 19 path.
Since is in a non-conducting state, no current flows. At this time, if the threshold voltages of the bit line load transistors 25a, 25b, 26a, and 26b are Vth, the potential of the bit line 20b through which no direct current flows is the potential of the power supply 18 -Vthq, that is, the precharge voltage. On the other hand, the potential of the bit line 20a through which the DC current flows is the value obtained by dividing the voltage between the voltage 18 and the ground 19 by the conduction resistors of the driver transistor 41a, the access transistor 42a, and the bit line load transistor 25a. Therefore, a value lower than the potential of the bit line 20b by a certain voltage ΔV, that is, the potential of the power supply 18 -Vth-
It becomes ΔV. Generally, ΔV is called the bit line amplitude, and is usually about 50 mV to 500 mV, and is adjusted depending on the magnitude of the bit line load. This bit line amplitude is transferred to I/O line 29a via transfer gates 27a and 27b.
and 29b. The sense amplifier 9 amplifies this, and the output buffer 10 controls the output and outputs it to the data output terminal 11. In other words, the bit line amplitude is read out as data output. Note that when reading data, the input data buffer 13 is connected to the read/write control circuit 1.
6, the I/O line pair 29a and 29b is controlled not to be driven. Therefore, referring to FIG. 8(C), the voltage levels of bit lines 20a and 20b become a low level and a high level, respectively, having a potential difference of bit line amplitude ΔV after equalization period t.

As described above, when reading is successively performed from the memory cells 24a and 24c that store mutually compatible data, the data output signal derived to the data output terminal 11 is as shown in FIG. 8(f). After a period t during which the bit line is equalized has elapsed from the time when the address signal changes, the bit line is inverted.

This type of bit line equalization is performed when reading data from memory cells is performed continuously, and when data complementary to the previous successive data is read, the voltage level applied to the bit line by the previous read is This is done in order to prevent it from taking time for the bit line to reach the voltage level to be applied by the current read because it is held for a while.

Next, the operation of the SRAM during data writing will be explained. For example, when inverted data of the stored data is written into the memory cell 24a in FIG. 6, the memory cell 24a is first selected by the same operation as in reading, and then the bit line
If a and 20b are at low level and high level, respectively, the data buffer 13 is connected to one I/O line 2.
9a to high level and the other I/O line 29b to low level. As a result, the bit lines 20a and 20b are forced to a high level and a low level, respectively, and the inverted data of the previously stored data is newly written into the memory sensor 24a.

By the way, although an inverter is used for the equalize buffer 32 in FIG.
2 buffers the one-shot pulse (equalization control signal) from the ATD circuit 17, and derives a signal that makes the equalizer corresponding to at least the selected memory cell conductive during the period when the one-shot pulse is output when data continues to be output. Any circuit is fine.

Now, as the capacity of semiconductor memory devices has increased in recent years, the number of memory cells has increased, so in current large-capacity SRAMs, the memory cell array is generally divided into several subarrays, and each subarray has a row decoder, a column decoder, and a column decoder. Peripheral circuits such as a decoder and an equalization buffer are provided as necessary, and these constitute one block. In such an SRAM, a block selection signal BS is applied to each block as an external signal for selecting which block of memory cells is to be accessed. Generally, when the block selection signal BS is at a high level, the block is selected. Therefore, each equalize buffer in the SRAM divided into blocks receives the equalize control signal EQ and block selection signal B output from the ATD circuit.
A circuit that takes logic with S may also be used. Figure 2 shows some examples of logic circuits used as equalizer buffers in such cases.
FIG. 2 is a diagram using logic symbols to represent a case where a channel MOS} transistor is used. Figure 10(a)
When the two-man power NAND gate 901 is used as an equalization buffer, it is sufficient to apply the equalization control signal EQ and the block selection signal BS to its input.

Referring to FIG. 10(b), when a two-man powered NOR gate 902 is used as an equalization buffer, the equalization control signal EQ and the inverted block selection signal BS may be applied to the two-man powered NOR gate 902. Referring to FIG. 10(C), when a series connection of a two-man power NAND gate 901 and an inverter 903 is used as an equalization buffer, an inverted signal EQ of the equalization control signal EQ and a block It is sufficient if the selection signal BS is given. No matter which of the logic circuits shown in FIGS. 10(a), (b), and (c) is used as the equalize buffer, when the block selection signal BS becomes high level, that is, the equalize buffer When the block connected to is in the selected state, the output voltage of the equalize buffer is as follows: when the equalize control signal EQ becomes high level,
That is, it becomes low level only when a one-shot pulse is generated from the ATD circuit. In other words, in response to a one-shot pulse from the ATD circuit, a one-shot pulse is given that makes only the equalizer provided in the selected block conductive.

Figure 10 shows an S made up of four blocks using N-channel MOS transistors as equalizers.
FIG. 2 is a simplified partial schematic block diagram of a RAM. Referring to FIG. 10, subarrays AO, AI, A2, and A3
row decoders LO, Ll, L2
, and L3, column decoders CO, CI, C2, and C
3. Two-man AND gate EO as equalization buffer
, El, E2 and E3 are provided. An equalization control signal EQ from an ATD circuit 17 is commonly applied to one of the human power terminals of each of the equalization buffers EO, El, E2, and E3. Equalize buffer E
The other end of each of O, El, E2, and E3 receives corresponding block advance selection signals BSO, BSI, and BS.
2, and BS3 are given. Therefore, in this case, in response to the generation of the equalization control signal from the ATD circuit 17, only the equalization buffer provided in the block whose block selection signal is at a high level and is in the selected state is used to select the equalizer included in that block. A one-shot pulse is output that makes conductive.

In addition to the address clock method (see Japanese Patent Publication No. 56-19587) in which the bit line is equalized by detecting changes in the address signal, the column decoder is a column switch MOSFET (first
In the figure, they correspond to transistors 27a and 27b and 28a and 28b. There is a method (see Japanese Patent Laid-Open No. 62-26692) that uses an equalizer that receives a signal supplied to the column switch and becomes conductive based on the non-selection level voltage of the signal (voltage at a level that turns off the column switch). In this method, one signal line is connected to each equalizer, which connects the column switch MOSFET provided in the corresponding column and the column decoder, unlike the method described above. be done. That is, a signal obtained by decoding a column address signal is used as a signal for controlling ON/OFF of each equalizer.

Therefore, bit line pairs corresponding to all memory cells that are not in a selected state are always equalized in preparation for reading.

[Problems to be solved by the invention] Conventional S that performs equalization using an address clock
The same number of equalizers as the number of bit line pairs included in one block are connected to one equalization buffer in the RAM. On the other hand, as memory elements have become highly integrated in recent years, the number of memory cells in one block of SRAMs has been increasing. This means an increase in the number of columns in one block, that is, the number of bit line equalizers. Therefore, as memory devices become more highly integrated, the number of equalizers connected to one equalization buffer increases.

By the way, the equalizer switching speed (ON/OF
The time T required for switching F is proportional to the first power of the total load C coupled to the output end of the equalization buffer provided in the preceding stage. When a MOS transistor is used as an equalizer, the MOS transistor used as an equalizer
Assuming that the gate capacitance of one h transistor is co and the number of columns in one block is N, the total negative ztac coupled to the output end of the equalization buffer is expressed as NXCo.

Therefore, as the number of columns in one block increases, the total load on the equalization buffer increases, and as a result, the switching speed T of the equalizer increases, that is, the switching speed becomes slower. On the other hand, the conventional SRA as mentioned above
In M, reading data from a memory cell is always performed after the bit line pair corresponding to the memory cell is equalized by conduction of the equalizer. therefore,
When the switching speed of the equalizer decreases, the time required to equalize the bit line pair becomes longer, and as a result, after an address signal for selecting a certain memory cell is applied to the address signal input terminal of the SRAM, data is read from that memory cell. The time required for the data to be output to the data output terminal, that is, the access time to the SRAM increases. Generally, the equalizer switching speed T is
Size B of the equalize buffer provided before this
is inversely proportional to. Therefore, one way to solve this problem is to change the size (drive capacity) of the equalization buffer.
One possible method is to increase B. By the way, the increase in the size of the equalize buffer is due to the ratio of the size of the equalize buffer to the circuit that drives it, that is, the size of the gate provided in the front stage of the equalize buffer, that is, the fan of the gate provided in the front stage of the equalize buffer. This means that the out will be larger. Generally, when the fan-out becomes 4 to 5 times or more, the response speed to input of the next-stage circuit driven by the gate rapidly decreases. Therefore, even if the size of the equalization buffer is increased to avoid a reduction in the switching speed of the equalizer, it takes time for the equalization buffer to output the equalization control signal to the equalizer in response to the signal from the previous gate. As a result, the SRAM access time cannot be improved.

Generally, in order to avoid a decrease in the response speed of the next stage gate due to an increase in the fanout of the previous stage gate, several new gates are added between these gates so that the closer they are to the next stage gate, the larger the size of the gate. It is already known that the fan-out of each of these gates can be set to an appropriate value by providing . Therefore, in order to avoid the drop in response speed of the equalize buffer itself as described above, at least one gate is provided between the equalize buffer and the previous stage gate that drives it, so that the closer it is to the equalize buffer, the larger the size of the equalize buffer is. Gates may be provided and the fanout of each of these gates may be adjusted to a value that does not reduce the response speed of the gate at the next stage. However, in such a method, as the size of the equalize buffer increases, the number of gates that must be provided at the front stage of the equalize buffer increases. Such an increase in the number of redundant circuit elements is undesirable because it impedes high integration not only in SRAMs but also in semiconductor integrated circuit devices in general.

Further, even if it is possible to avoid a decrease in the response speed of the equalize buffer itself by the method described above, and to avoid a decrease in the switching speed of the equalizer by increasing the size of the equalize buffer, the following problem will occur. Since the current is the amount of moving electricity in a minute time, the peak current I flowing in the wiring connecting the equalization buffer and the equalizer is calculated by dividing the number of columns in one block by N1.
The total load of the equalization buffer is C (-NXCo),
The switching speed of the equalizer is T1. The amount of change in the equalizer gate voltage due to equalizer switching is VCC.
Then, it is expressed as ■#Cxvcc/T. Therefore, if the equalize buffer size B is increased to suppress an increase in the equalizer switching speed T in response to an increase in the number of columns N, that is, an increase in the total load amount C of the equalize buffer, the value of C/T will be As a result, the peak current (2) flowing through the wiring connecting the equalization buffer and the equalizer becomes large. That is, in this method, the value of C/T increases and the peak flow rate l increases in proportion to the increase in the number of columns N. Here, the equalization buffer and the equalizer are generally connected by a metal κ-ray layer made of aluminum or the like formed on a substrate. Migration, where metal atoms move inside the wiring layer as the current flowing through it increases, is likely to occur in such metal wiring layers.
An increase in the peak current I as described above has a high risk of causing a disconnection state in the wiring layer due to migration. Therefore, an increase in current density in the wiring connecting the equalization buffer and the equalizer as described above is not preferable from the viewpoint of reliability of the SRAM.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a static semiconductor memory device in which the access time is shortened and the access time is not increased due to the addition of memory cells.

[Means for Solving the Problems] In order to achieve the above object, a static semiconductor memory device according to the present invention includes a memory cell array divided into blocks each including a first plurality of complementary data line pairs; equalizing means for individually equalizing each of the first plurality of complementary data line pairs in each block or a group including a second plurality of pairs smaller than the first plurality.

[Operation] As described above, in the static semiconductor memory device according to the present invention, in each of the memory cell arrays divided into blocks, the first plurality of complementary data line pairs included therein are Each pair is individually equalized.

[Embodiment] FIG. 1 is a partial schematic block diagram showing an example of the present invention, showing the structure around an equalization buffer of an SRAM divided into blocks. Note that the construction of other parts of the SRAM not shown is as described in the prior art. Referring to FIG. 1, the equalize control signal EQ output from the ATD circuit 17 in response to changes in address signals from the row address buffer and column address buffer (not shown) is applied to each block as in the conventional case. After being buffered by one buffer (hereinafter referred to as a block buffer) provided in the block E, the signal is supplied to each block BL. However, in each block BL, unlike the conventional art, the equalization control signal is buffered by an equalization buffer e provided for one or more bit line pairs, and then sent to all equalizers 30 connected to the equalization buffer. supplied to Hereinafter, a collection of bit line pairs corresponding to equalizers connected to one equalization buffer, ie, a collection of columns, will be referred to as one column group. In this way, the equalization control signal generated when the address signal changes is supplied to the equalizer by the separate equalization buffers provided for each column group C in each block BL. ON
The number of equalizers to control /OFF is much smaller than in the past. In other words, the total amount of load coupled to the output end of one equalization buffer is reduced. This means an improvement in the switching speed of each equalizer. Therefore, after the address signal changes as the address of the selected memory cell changes, data is read from the memory cell (selected memory cell) corresponding to the address signal after the change, and this data is led out to the data output terminal. The time required for access (access time) to be accessed is shorter than before.

FIG. 2 shows a specific example of the embodiment shown in FIG.
2 is a partial schematic block diagram of a RAM, showing the configuration around an equalization buffer for one block of an SRAM divided into blocks. FIG. Specifically, in FIG. 2, two-man AND gates are used for the block buffer E and equalization buffer e in FIG. 3, an N-channel MOS transistor is used as the equalizer, and the number of column groups included in one block is two. , the number of columns included in one column group is 4
This is the case when Referring to FIG. 2, an equalization control signal EQ and a block selection signal BS are applied to a two-manual AND gate E provided as a block buffer for each block BL, and the two-man power AND gate E provided as a block buffer for each block BL is supplied with an equalization control signal EQ and a block selection signal BS. A two-man AND game provided as an equalization buffer corresponding to each el and e
2, the output of the corresponding block buffer E and the corresponding column selection signal (CGSI or C(;
';2) is given. Here, the column selection signal CGS
I is column group c1 corresponding to equalize buffer e1
This signal goes high when a memory cell to be selected is included in column group c2, and the column selection signal CGS2 goes high when a memory cell to be selected is included in column group c2 corresponding to equalize buffer e2. This is a signal. In this case, the one-shot pulse that makes the equalizers 30 included in the column group c1 conductive from the equalize buffer yel, that is, the equalize control signal, is output from the block selection signal BS corresponding to the block to which this column lcl belongs and the column nc1. When the column selection signals CGSI corresponding to both become high level, the equalize control signal E is output from the ATD circuit 17.
Only when Q occurs. Similarly, from equalize buffer e2, equalizer 3 included in column 11 (2)
The one-shot pulse that makes 0 conductive is output because
Only when the equalize control signal EQ is generated from the ATD circuit 17 when the block selection signal BS corresponding to the block to which this column group C2 belongs and the column selection signal CGS2 corresponding to the column group c2 are both at high level. be. Therefore, the equalize control signal EQ generated from the ATD circuit 17 in response to the address signal being reduced equalizes all bit line pairs within the column to which the memory cell to be selected by the changed address signal belongs.

Column address signals, which are external signals, may be used for column selection signals CGS1 and CGS2, for example, similarly to block selection signal BS.

For example, in the example shown in FIG. 2, the total number of RAMs in one block is 8, so the column address signal in this case is 3-bit data. Therefore, the address signal when any one bit of these three bits YO, Yl, and Y2 is O representing the low level t= sign, and the address when it is 1 representing the /\I level signal. Each signal corresponds to four columns within one block. In the example shown in FIG. 2, the number of columns included in one column group is four, so for example, two column groups C1 and C2 in one block are each one of the three bits that groove the column address signal. When corresponding to a column address signal in which Y2 is 1 and a row address signal in which Y2 is 0, column address signal Y2 and its inverted signal y2 may be used as column group selection signals CGS1 and CGS2, respectively. As a result, when the memory cell included in column B$cl is selected, the column selection signals CGS1 and CGS2 become high level and low level, respectively, and when the memory cell included in column group c2 is selected, the column selection signals CGS1 and CGS2 become high level and low level, respectively. selection signal CG
SI and CGS2 become low level and high level, respectively. In other words, the equalize control signal can be generated only from the equalize buffer corresponding to the column group including the selected memory cell. Therefore, only the bit line pairs to be equalized (when the number of columns included in one column group is 1) or all the bit line pairs belonging to the column group including the bit line pair to be equalized are equalized when selected. be done. by this,
Since the current flowing through the bit line pair that needs to be equalized is reduced compared to the conventional case, a favorable effect of reducing power consumption is brought about. Note that the configurations around the equalize buffers for other blocks not shown are also the same.

In the above embodiment, the equalize buffer 7 provided for each column group of each block is a two-man AND gate, but the logic gate used as the equalize buffer is not limited to this. FIG. 3 is a diagram showing a specific example of an equalize buffer using logic symbols when a P-channel MOS transistor is used as an equalizer, and shows another embodiment of the present invention.

Referring to FIG. 3(a), when a two-man power NAND gate 301 is used as an equalizer sofa, the equalization control signal EQ' from the block buffer, which is a high-level one-shot pulse, is input to its input. It is only necessary to provide a column group selection signal CGS which becomes high level when a memory cell to be selected is included in the column group corresponding to this equalize buffer. Figure 3 (b
) and use the two-man NOR as an equalization buffer.
When the gate 302 is used, GS may be supplied manually by the equalize control signal EQ' from the block buffer and the inverted signal of the column selection signal CGS. Referring to FIG. 3(C), a two-man NAND gate 301 and an inverter 303 are used as an equalization buffer.
When a series connection is used, the inverted signal EQ of the equalization control signal EQ' from the block buffer and the column selection signal C are input to the two-man NAND gate 301.
It is sufficient if GS is given. According to the equalize buffer shown in FIGS. 3(a) to (C), the column group selection signal C
Only when GS is at a high level, that is, when the column group corresponding to the equalize buffer includes a memory cell to be selected, is the equalize buffer low in response to the generation of the equalize control signal EQ from the ATD circuit. A level one-shot pulse occurs.

Therefore, only the bit line pairs in the column group containing the selected memory cell are selectively equalized.
Power consumption is reduced.

In all of the above embodiments, a block buffer is provided between the equalize buffer provided for each column group and the ATD circuit, but this block buffer is not necessarily required. The size may be made slightly larger than in the above embodiment, and the block buffer may be removed. Figure 1 shows one block-divided SRAM in such a case.
FIG. 3 is a partial schematic block diagram showing the internal structure of the block.

Note that the overall configuration of this SRAM is the same as the conventional one. Specifically, for the sake of simplicity, FIG. 1 shows a configuration around a memory cell array when memory cells are arranged in a matrix of 2 rows and 2 columns within one block.

Referring to FIG. 4, word line 22 connected to row decoder 6 includes a memory cell 24g provided between bits 1120a and 20b constituting a bit line pair, and another memory cell 24g provided between bits 1120a and 20b forming a bit line pair.
Bit lines 21a and 21b forming one bit line pair
A memory cell 24b provided between the bit lines 1920a and 20b is connected to the word line 23, and a memory cell 24d provided between the bit lines 21a and 2lb is connected to the word line 23. Connected. Bit lines 24 a, 24 b, 24 C and 2
Bit line load transistors 25a, 25b, 26a, and 26b are provided between 4d and power supply 18, respectively. A P-channel MOS is connected between the bit lines 20a and 20b as an equalizer to short-circuit them.
A transistor 30a is provided and similarly bit line 21
P channel M is used as an equalizer between a and 2lb.
An OS transistor 30b is provided. The transistor 27a, which is a transfer gate, is an I/O transistor connected to the bit line 20a1, the sense amplifier 9, and the human buffer 13.
Transistor 27b, which is provided between lines 29a and is a transfer gate, is connected to bit line 20a and I/O line 29 connected to sense amplifier 9 and human cover 713.
provided between b.

Similarly, transistor 28a which is a transfer gate
are the bit lines 21a and ! Transistor 28b, which is a transfer gate, is provided between bit line 21b and two I/O lines b. The gates of transistors 27a and 27b and the gates of transistors 28a and 28b are connected to column decoder 5 by different signal lines. The data input terminal 12 is connected to the input buffer 13, and the output terminal of the sense amplifier 9 is connected to the data output terminal 11 via the output buffer 10. The above structure is the same as the conventional one.

However, unlike before, the equalizers 30a and 30
An equalization buffer for supplying an equalization control signal for controlling the ON/OFF of b to the gates of equalizers 30a and 30b is provided individually for each equalizer. That is, an inverter 32a is provided as an equalize buffer between the gate of the equalizer 30a and the equalize control signal input terminal 31, and the equalizer 30a
An inverter 32b is provided as an equalization buffer between the gate of the input terminal b and the equalization control signal input terminal 31.

Note that the roles and operations of each of the above-mentioned functional units and the means for generating the equalization control signal are as explained in the "Prior Art" section. Therefore, when the address of the memory cell that is selected in succession changes, the ATD circuit 17 in FIG.
) is generated and applied to the equalize control signal input terminal 31.

This equalize control signal is transmitted to the equalize buffer 32a.
and 32b, and one is co-fed to the gates of equalizers 30a and 30b. In other words, the number of equalizers whose ON/OFF should be controlled for one equalization buffer is one. Therefore, the total negative Q fit coupled to the output end of one equalization buffer is reduced, and the switching speed of each equalizer is improved. As a result, the time from when the address signal changes due to the address change of the selected memory cell until data is read from the memory cell corresponding to the changed address signal and this data is led out to the data output terminal 11. (access time) is shortened.

However, an actual memory cell matrix includes a very large number of equalizers. Therefore, in this embodiment, 1
Although an equalization buffer is provided for each equalizer in a block, one equalization buffer may be provided for a plurality of equalizers as in the previous embodiment. Of course, the number of equalizers connected to one equalizer buffer in this case should be set to such an extent that a reduction in the switching speed of these equalizers does not pose a problem. Furthermore, in this embodiment, when the address signal changes, the equalize control signal is given to the equalizers corresponding to all columns of all blocks.
Bit line pairs corresponding to all columns are equalized. However, in operation, only the bit line pair corresponding to the memory cell to be selected by the changed address signal needs to be equalized. Therefore, similarly to the block buffer and equalize buffer in the embodiments shown in FIGS. 2 and 3, the logic The gate may be used as an equalization buffer, and the equalization control signal may be supplied only to the equalizer corresponding to the column group to which the memory cell to be selected belongs.

According to the present invention, the total number of equalize buffers is increased compared to the conventional one, but since the total load amount of one equalize buffer is small, the size of each equalize buffer in the present invention may be relatively small. Therefore, the increase in the number of equalization buffers according to the present invention does not impede higher integration of memory cells and the like.

[Effects of the Invention] As described above, according to the static semiconductor memory device of the present invention, the total load of the buffer means provided immediately before the equalizer that equalizes the Aigaki data line pair in the conduction 1 (:j) is reduced. Therefore, the equalization speed of the FI1 complementary data line pair is improved, and as a result, the access time of the static semiconductor memory device is shortened.

[Brief explanation of the drawing]

FIG. 1 is a partial schematic block diagram of an SRAM showing an embodiment of the present invention, FIG. 2 is a partial schematic block diagram of an SRAM showing a specific example of the embodiment shown in FIG. Logic circuit diagram showing an equalize buffer in another embodiment, FIG. 4 is an SRAM showing still another embodiment of the present invention.
5 is a schematic block diagram showing the overall configuration of SRAMs according to the conventional technology and the present invention. FIG. 6 is a partial schematic block diagram of conventional SRAMs. FIG. 7 is a partial schematic block diagram of SRAMs according to the conventional technology and the present invention. FIG. 8 is a circuit diagram showing the internal structure of the memory cell in the conventional and the present invention.
A waveform diagram for explaining the operation at the time of AM reading, FIG. 9 is a logic circuit diagram showing another example of an equalize buffer in a conventional SRAM, and FIG. 10 is a simplified configuration of a conventional SRAM with a block division structure. FIG. In the figure, 1 is a memory cell matrix section, 2 is a row address input terminal, 3 is a column address input terminal, 4 is a row address buffer, 5 is a column address buffer, 17 is an ATD circuit, 20a and 20b, 21a and 21b. u is a bit line pair, 30, 30a and 30b are equalizers,
32.32a32b, e, el, e2, and EO-E
3 is the equalization buffer, E is the block buffer, B
L is one block, AO to A3 are each one subarray, c,
cl and C2 each indicate one column group. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 3 3oJ: NAUD Kenito 3o:z: NORτ2L 3o3゜1 I〉8″-7 Figure 7 (a) Figure 17 (b) Figure 8 Close 2L-Yo. .r 24 cl. Indication of the case 2. Title of the invention 3. Amended Patent Application No. 1-150865 Static semiconductor memory device 5. Detailed description of the invention in the specification to be amended , Figures 4, 5, 6 and 8 of the drawings 6, Contents of amendment (1) "Leave it alone" in line 7 of page 2 of the specification is corrected to "leave it alone" do. (2) Correct "row address buffer 5" in the 6th to 7th lines of page 3 of the specification to "column address buffer 5." (3) Correct "chip select signal" in lines 3 and 9 of page 4 of the specification to "chip select signal." (4) Correct "chip selector input terminal" in lines 3 to 4 and line 8 of page 4 of the specification to "chip select input terminal." (5) "Basically, it is not necessary..." in lines 4 and 5 of page 5 of the specification shall be corrected to the following sentence. Basically, it is possible to perform the original function of writing and reading data without applying an internal synchronization signal. Correct. (7) "Chip selector input terminal" on page 14, line 14 to line 15 of the specification as "chip select input terminal"
Correct. (8) "Therefore, . . . is equalized." on page 17, line 9 to line t2 of the specification is corrected to the following sentence. Furthermore, the equalization signal (the one-shot pulse) from the ATD circuit 17 is also supplied to the equalizers of the I/O lines 29a and 29b and the equalizer of the output of the sense amplifier 9, The output of is also equalized. (9) Change “high level” on page 17, line 16 of the specification to “
Correct to "low level". (10) “And 45b” on page 18, line 17 of the specification
and delete “respectively.” (11) "Figure 2" on page 23, line 12 of the specification is corrected to "Figure 9." (12) Change “Figure 10” on page 23, line 17 of the specification to “
Figure 9 has been corrected. (13) Page 24 of the specification, lines 1, 5, and 11
Correct "Figure 10" in the line to "Figure 9". (■4) Change “Fig. 1” on page 26, line 9 of the specification to “Fig.
Corrected to ``Figure''. (15) Specification page 27, line 17, page 28, line 8,
"Page 29, line 1, page 31, line 10, and line 16"
Correct "switching speed" to "switching time". (16) In the specification, page 31, line 6, "amount of charge transferred in a minute time" is corrected to "amount of charge transferred in a unit time." (17) "Peak current I" on page 31, lines 8 and 19 of the specification, and on page 32, lines 1 and 7, is corrected to "charging/discharging current I." (18) "Unnecessary bit line" on page 39, line 9 of the specification is corrected to "unnecessary bit line." (19) On page 41, line 15 of the specification, “provided” was replaced with “
Corrected to "provided for." (20) Specification page 41, line 17 and page 42, line 1
Correct the line ``Figure 1'' to ``Figure 4''. (21) "Figure 6" on page 44, line 15 of the specification is corrected to "Figure 5." (22) Figures 4, 5, 6, and 8 of the drawings are corrected as shown in the attached sheets. that's all

Claims (1)

Claims: A memory cell array including a plurality of complementary data line pairs, the memory cell array being divided into a plurality of blocks, each block including a first plurality of complementary data line pairs, A static semiconductor further comprising equalizing means for individually equalizing each of the first plurality of complementary data line pairs in each block or a group including a second plurality of pairs smaller than the first plurality. Storage device.