JPH0316094A - Dynamic type semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a memory element of 1.5 element per 1 bit and to contrive a high integration by storing the information of 2 bits in a memory cell by positive and negative of the polarity and two kinds of accumulation charge quantities. CONSTITUTION:The dynamic type semiconductor memory is provided with a first and a second complementary bit lines offered for an input and an output of information, an accumulation capacity means 11 for storing the information, and a first and a second selecting means 12, 13 for designating the accumulation capacity means, and has a memory cell structure for connecting one end of the accumulation capacity means 11 through a first selecting means to a first bit line of the complementary bit lines, and connecting the other end of the accumulation capacity means 11 to a second bit line of the complementary bit lines through a second selecting means 13. In this state, information of a quarternary, namely, 2 bits is stored. In such a way, a memory element of 1.5 element per 1 bit can be realized, and a high integration is contrived.

Description

[Detailed Description of the Invention] Industrial Application Fields The present invention relates to improvement of a dynamic semiconductor memory device, and more particularly, to a device equipped with a novel structure that enables high performance of a dynamic memory element. This relates to a dynamic semiconductor device.

Conventional technology> In recent years, the integration of dynamic semiconductor memory devices has progressed at a tremendous pace, but only one bit per bit! ) 2 elements (l
}The memory sensor structure (one resistor and one capacitor) has not changed.

FIG. 2 is a circuit diagram showing the structure of a conventional dynamic semiconductor memory device.

In the figure, 20 is a conventional memory sensor (1
2l is a storage capacitor, 22 is a transfer gate serving as a selection means, and 23 is a storage node.

On the other hand, there is a restriction that the storage capacity of the capacitor cannot be made even smaller due to reliability Q points such as soft errors.

Therefore, in order to achieve high integration in recent years, the main approach has been from a process perspective, how to secure the minimum necessary storage capacity in a small area. Memory cells of type, stacked type, or combinations thereof have been developed.

Problems to be Solved by the Invention> However, such three-dimensional memory cells have many problems in the manufacturing process, and require a long development period to ensure high reliability.

The present invention has been made in view of the above-mentioned problems.
The purpose of this invention is to provide a memory element that stores 2 bits of information using three elements: a transistor and an 1-capacitor with the same storage capacity as the conventional one, that is, 1.5 elements per 1-bit.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

Means and Effects for Solving the Problems> A brief summary of the invention disclosed in this application is as follows. That is, it includes complementary first and second bit lines for inputting and outputting information, storage capacitor means for storing information, and first and second selection means for specifying the storage capacitor means. One end of the storage capacitor means is connected to the lth bit line of the bit line of It has a memory cell structure connected to the second bit line of the line, and stores four-valued information, that is, two pits, with positive and negative polarity and two types of accumulated charge amounts in the memory cell. The feature is that a memory cell with v1.5 elements per bit can be realized with a read margin higher than that of the conventional method.

Embodiment> FIG. 1 is a circuit diagram for memory cells and reading and writing of a dynamic semiconductor memory device showing an embodiment of the present invention.

FIG. 8 shows input timing waveforms to explain the operation of the circuit shown in FIG. 1, and FIGS. It shows.

In the figure, 10 is a memory sensor (
2 bits), 11 is the storage capacity, 12.13 is the transfer game serving as the first and second selection means}, 14, 15
is the storage node, 16.17 Pasenne amplifier.

The operation of the circuit shown in FIG. 1 will be explained below.

Here, word line WLL+ and bit lines BLLI, B
(1) of memory cell/L/l Q selected by LLI
Consider read, (2) rewrite, (3) precharge, and (4) write operations.

FIG. 3 shows input timing waveforms for explaining the operation of FIG. 1.

Fi+ Read operation When the button is pressed at time to in Figure 3 and NEQ and PEQ change as shown in the figure, all transistors in the bit line equalization circuit in Figure 1 are turned off, bit line precharging is completed, and the The voltage also becomes 1/2Vcc.

Next, BLLI. Memory seven stories connected to BLLI 1
When 0 is selected, the transistor of CUT 2 is turned off,
Word line WLLI is activated at time t1.

Then, the information stored in the storage capacitor 1l is transferred to the bit lines BLLI, BLRI, SBLI. Charge is transferred to SBL2.

Furthermore, when CUTI and REQ fall at time t2, the bit line and sense amplifier on the memory cell side are disconnected, and SBLI and SBL2 and SBL1 and SBL2 are also disconnected. This means that sense amplifiers l6 and 17 have the same information of memory cell/v10 separately.

Therefore, after changing UP and DOWN as shown in Figure 3 at time t3, the sense amplifier operation by SAS starts at time t4, and at time t5, CUTI and CUT2 are started to connect the sense amplifier and the bit line on the memory cell side. Connect to perform pull-up by SAS.

Finally, at time t6, CSEL is turned down, the amplified information in the memory cell is transferred to the data line, and the read operation is completed.

Note that the bit lines SB Ll and SBL at time t3
1 and SBL2. The SBL2CI changes are detailed below.

Since the memory cell of the present invention stores two hits of information in one storage capacitor, the voltage state a of the storage nodes 14 and 15 when holding the memory cell information is shown in Table 1 below. There are four types of lines.The data in the table is the data line DI.
It corresponds to the voltage output to D2.

Table 1 Among these, DI=H. FIG. 4 shows the state when reading the information of D2=H, and FIG. 5 shows the state when reading the information of D I =H-, 'D2=L. D
I=L. If D2=L, if you replace SEL2,
In addition, in the case of DI=L, D2=H, SBLI is
Since they are equivalent if SBLI and SBL2 and SBL2 are replaced, only the former two will be explained.

1. When reading the information of DI=H, D2=H, the fourth
As shown in the figure, at time t1 when the word line rises, a potential difference of AV occurs between each complementary bit line pair. Time t
3, by the UP and DOWN signals, SBLI,
The potential of SBL2 is increased by 1/3 JV, while SB
The potential of LISBL2 is lowered by 1/3JV.

However, S BLI and SBLI, and SBL2 and SBL
The voltage of DI.2 does not reverse, and after the sensing operation after time t4, the voltage of DI. Vcc level is output from both D2.

On the other hand, when reading the information of DI=HゎD2=L, the fifth
As shown in the figure, at time ti when the word line rises, only a potential difference of 1/3 dV occurs between each complementary bit line pair. Therefore, at time t3, the potentials of SBLI and SBL2 are raised by 1/3 JV by the UP and DOWN signals, while the potentials of SBLI and SBL2 are lowered by 1/3 dV, and the potentials of SBL2 and SBL2 are , and do it in reverse. Therefore, after the sensing operation after time t4,
Vcc is output to DI, and GND level is output to D2.

Note that the value of I73JV is, where CB is the parasitic capacitance of the bit line and CS is the storage capacitance of the memory cell, and CB/C
When the S ratio is 2 or more, this is much larger than the value in the conventional method that uses CS for 1 bit, and considering that the practical CB/CS ratio is around 10, it is difficult to read the bit line. It can be seen that the voltage, that is, the read margin, is better in the present invention.

(2) Rewriting operation At time t7 in FIG. 3, CSEL is brought down and the voltage line is disconnected.Furthermore, at time 73, CUT1 and CUT2 are brought down and the sense amplifier is also disconnected.

After making the bit line on the memory cell side floating in this way, BLS2 is brought down at time t9, and the memory cell l
The bit lines BLL2, BLR2 and BLL2, BLR2 on the side to which O is not connected are divided into two.

After that, at time tlo, WEQL on the side to which memory cell #10 is connected is brought down, and BLL2 is connected to BLL1 and BLR.
Also connect BLL2 to BLLI and BLRIK to I.

As a result, the potential changes as shown in Table 2 below, and the same voltage as before the word line was turned on is written to the storage node 14.15 of the selected memory cell/L/10, and the storage capacitor 1L is , a charge corresponding to that voltage is stored.

Table 2 In this way, the word line WLL+ falls at time tll, and the rewriting is completed.

(3) Precharge operation In the precharge that continues, at time tl2, UP, DOWN
．． BLS2, WEQL. Return NEQ and PEQ to the initial state of the cycle, set the voltage of the bit line on the memory cell side to 1/2Vcc by charge division, and set SAS and SAS to the initial state of the cycle.
Return to 1/2Vcc and stop the sense amplifier.

Finally, at time 113, CUTI, CUT2, and REQ are raised to complete the precharge operation.

(4) When reading a write operation, CSEL is started at time t6 in FIG. 3! In this case, the data line is floating. On the other hand, during writing, this data line is fixed to H (Vcc ~ L (GND)) of write N write data, and after time t6, the read data on the bit line is replaced with this write data. It will be done.

After time t7, new information is written into the memory cell by the same operation as in rewriting (2).

FIG. 6 shows a second embodiment. The difference from FIG. 1 is that there is no need for a transistor whose gate is WEQR in the write circuit. SAS, SAS of the sense amplifier
'e Two types are prepared for each sense amplifier (SASI,
By delaying the operation of SAS2, SEL2. SBL2
You can only push.

FIG. 7 shows a third embodiment. The difference from FIG. 6 is that the readout circuit is SBL2. Can boost SLB2 and SBL I. SLBI can also be boosted. Further, the transfer gates of the bit line sense amplifier isolation circuit and the write circuit are complementary types.

Effects of the Invention As described above, according to the present invention, a memory cell with 1.5 elements per bit can be realized with a read margin higher than that of the conventional technology, which greatly contributes to higher integration of dynamic semiconductor memory devices. It is something.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the structure of a first embodiment of the present invention;
FIG. 6 is a circuit diagram showing the structure of a second embodiment of the present invention;
FIG. 7 is a circuit diagram showing the structure of a third embodiment of the present invention;
FIG. 2 is a circuit diagram showing the structure of a conventional dynamic semiconductor memory device, FIG. 3 is an input timing waveform diagram for explaining the operation of FIG. 1, and FIGS. 4 and 5 are similar diagrams. FIG. 1 is a diagram showing waveforms during readout of bit lines for explaining the operation of the circuit shown in FIG. 1; Explanation of symbols lO2 Memory cell/v (2 bits) according to the method of the present invention
, l1: Storage capacity, 12, l {: Transfer game serving as first and second selection means}, 14. l5: storage node, 16.17: sense amplifier, 20: memory cell/v (1 bit division) by conventional method, 2l: storage capacity, 22:
Transfer gate serving as selection means; 28: storage node;

Claims (1)

[Claims] 1. Complementary first and second bit lines for inputting and outputting information, storage capacitor means for storing information, and first and second selection means for specifying the storage capacitor means. one end of the storage capacitor means is connected to the first bit line of the complementary bit lines via the first selection means, and the other end of the storage capacitor means is connected to the first bit line of the complementary bit lines via the second selection means. The memory cell has a structure in which the memory cell is connected to a second bit line of the complementary bit lines, and the memory cell stores four values, that is, two bits of information, with positive/negative polarity and two types of accumulated charge amounts. A dynamic semiconductor memory device characterized by: 2. Apply different voltage changes to the complementary first and second bit lines, and change the potential difference read from the memory cell to a small amount if the amount of charge stored in the storage capacitance means is large. 2. The dynamic semiconductor memory device according to claim 1, wherein the cases are reversed. 3. A first differential amplifier is connected to the complementary first and second bit lines through a third selection means, and a second differential amplifier is connected to the complementary first and second bit lines through a fourth selection means. , a first bit line connected to the first bit line via a third selection means.
giving different voltage changes to the input of the differential amplifier, the input of the second differential amplifier connected via the fourth selection means, and the other input of each differential amplifier; Then, the potential difference read from the memory cell is unchanged if the amount of accumulated charge in the storage capacitor means is large, and if it is small, the potential difference at the input of either the first or second differential amplifier is reversed. 2. The dynamic semiconductor memory device according to claim 1, wherein