JPH0316143A - Method of operating charge coupled device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for operating a charge-coupled device, and more particularly to a method for operating a floating gate amplifier at the output of a charge-coupled device, which enables non-destructive readout. This is about how to do it.

Charge coupled devices (CODs) require low noise detection and amplification of signals represented by charge packets so that the COD can be used for low light level or other small signal applications.

Non-destructive readout is also a desirable method in order to allow the signal to be reprocessed even after the ffl signal has been detected. A typical amplifier U precharge amplifier for detecting charge packets.

This is a method in which the P-N junction is charged to a preset level through a MOS transistor, and then the signal charge is discharged to discharge the diode, thereby generating a current Lt proportional to the signal charge. . Unfortunately, the BRITCH amplifier destroys charge packets for subsequent processing, and also generates a noise voltage proportional to less than 500m due to thermal noise in the MoS transistor channel. Floating gate amplifiers that enable non-destructive readout were published in February 1973 at the International Solid State @
On pages 154-155 of the Preliminary W & Collection of the Road Conference ([SSCC)], Wen and Crape Myrtle (
ry) entitled "Analysis and Design of Single-Stage Floating Gate Amplifiers" and also published in the IEEE Journal of Solid-State Cir, published in December 1974.
Hen makes a presentation entitled ``Design and operation of floating gate amplifier'' in Vol. SC-9, No. 6, pp. 410-414 of ``Flying Gate Amplifier''.

This benefit also reduces the preset noise inherent in preset amplifiers. Its structure is t:'! The floating gate is recessed into an oxide layer below a large bias gate used to transfer the voltage below the 'it' gate. Clocking the bias gate to transfer voltage bound packets introduces noise on the floating gate and applies large voltages that stress the insulating oxide. Masayoshi type floating gate amplifier is 1
U.S. Patent Application No. 021,058, dated March 16, 979
Bow, Joseph E. Hall (Joseph E Hal
It is shown in ``Capacity coupled FIT1 gate amplification 4'' in 1). This modification places the bias gates apart and uses the υ1 control gate to transfer the charge packets, thereby increasing the sensitivity of the device and reducing some of the noise on the >1 stray gate. However, all of these structures lack electrical connections to the floating gate. Potential control on floating gates tends to be unstable. That is, the potential tends to drift over time due to the movement of charge in the surrounding insulator. This drift changes the operating point of the amplifier and CO
It also changes the potential of the D channel.

The method of the invention is embodied in a method using floating gate amplifiers for charge viscosity devices capable of non-destructive readout. Floating game 1 ~ is embedded in Zettai Rv4,
Defined by lower metal traces that intersect charge transfer channels. - In an embodiment, the floating gate is connected to the source of a metal monoxide-semiconductor transistor, the drain of which is connected to an upper level conductor that is a bias line. In another embodiment, the anode of the diode is connected to the floating gate and the cathode of the die A'' is connected to the bias line. The upper level metallization provides a pair of fdltll gates, which are connected to the floating gate. is adjacent to and partially overlaps the floating gate where it intersects the charge transfer channel. Charge packets are transferred under the floating gate by using a control gate. The control gate also The charge induces a voltage on the floating gate, which is detected and amplified. The output of the amplifier is connected to the charge under the floating gate. By electrically connecting the floating gate to the bias line through a resistive path, long-term drift in the floating gate set point is virtually eliminated in floating gate amplifiers constructed in accordance with the present invention. Ta.

The noise on the floating gate that occurs when presetting the floating gate to a predetermined voltage H can be reduced by presetting only when one or two readings are completed, instead of presetting every time a readout is performed. minimized. The synchronous clock noise induced into the floating gate by resistive coupling of the control gate is canceled by providing a suitable synchronous signal to the control gate. By using low signal levels and simplifying noise-canceling electronics,
The sensitivity of the device is improved.

The novel features of the invention are set forth in the claims. However, the invention itself, as well as other features and advantages thereof, will be best understood from the detailed description taken in conjunction with the following drawings.

Referring to FIGS. 1 and 2a-2d, there is shown a 1TI gate amplifier located at the output of a charge-coupled device used in the present invention. The actual floating gate amplifier is included within the dashed line in FIG. 1, and other output circuits are outside the dashed line. The floating gate amplifier is n
Mold silicone or other half-tempered materials may be used, but
It is formed in a veneer of semiconductor material 10 of first grade 4 y4+4, preferably P-type silicon. Implantation of a second conductivity type opposite to the first conductivity type forms a buried charge transfer channel 11 in the substrate 10 parallel to the semiconductor surface. The substrate 10 includes a pair of diffusion regions 12.1 of a second conductivity type.
3 are formed in the substrate 10 adjacent to the charge transfer channels 17 and the source 1 of the output transistor 14.
2 and a drain 13 are formed. The load resistor 15 is connected to the board 10
However, it is part of the diffusion region 1l112 which is the source of the output transistor 14. An insulator 16, preferably silicon oxide, is mounted over the substrate surface, over the transfer channel 11. In terms of manufacturing process, this insulator 16 is manufactured through one or more steps.

An elongated conductive member is embedded in insulator 16 to define floating gate 17 . One end of the floating gate extends across channel 11.

In a preferred embodiment, this conductive material portion 17u may be aluminum, in which case a portion of insulator 16 may be anodized aluminum. However, other materials such as polycrystalline silicon may be used instead of aluminum. Floating gate 17 also serves as the gate of output transistor 14.

A pair of IJ conductive phase electrodes 20.21 are embedded in the insulation gap 16 on the picture side of the floating gate and extend across the channel 11. A pair of parallel spaced IllwJ gates 22.23 of conductive material are mounted on the insulating gap 16 extending across the channel 11 and partially connected to the floating gate 17 and the phase II4i 20.21. It's getting busy. A pair of spreading regions 18 , 19 of a second conductivity type opposite to that of the substrate 1o are formed in the substrate 10 remote from the charge transfer channel 11 to form the source 18 and drain 19 of the floating gate bias transistor 27 . do. Floating gate 17 is connected to the source of floating gate bias transistor 27 through an electrode window in oxide f130 over source 18. A conductive member 28, preferably aluminum, is embedded in the insulation 1116 and forms the gate of the floating gate bias transistor 27. A bias line 29, preferably aluminum, connects the drain 19
It is connected to the drain 19 of the floating gate bias transistor 27 through an electrode window in the upper oxide layer 30. Conductive member 28 also functions as a control pulse line.

The silicon oxide 13130 is the source 12.18 of the output transistor 14 and the floating gate bias transistor 27.
and the drain 13, 19, and the load resistor 15. A thick field oxide region 31 is provided over a channel stop 32 of the same conductivity type as the substrate 10, surrounding the amplifier elements.

The source 12 of the output transistor 14 is a floating gate amplifier SZ
It also forms the drain 33 of the sample-and-hold transistor 35. The source 34 of the sample-and-hold transistor 35 and the source 40 and drain 41 of the sampled output source follower transistor 42 are diffusion regions of the same conductivity type as the diffusion region including the source region 12 and drain region 13 of the output transistor 14. . A conductive strip 43, preferably aluminum, is embedded in the insulator 16 and forms the gate of the sample and hold transistor 35. Strip 43 is the same material as floating gate 17 and is formed at the same time. Another conductive strip 44, preferably aluminum, is coupled through an electrode window in oxide EI 30 over source 34 to source 34 of sample-and-hold transistor 35 and also to the gate of sampled-out source follower transistor 42. It also takes shape. A thin section 26 of the insulation layer 16 that shapes the gate oxide 26 for all transistors.
-L is covered by the gate 44. Another load resistor 45 is provided in the substrate 10 , this negative resistor 45 being a fraction of the same diffusion region 40 that is the source of the sampled output source follower transistor 42 . A conductive member 46, preferably aluminium, is connected to the source 40 of the source follower transistor 42 through an electrode window in the oxide surround 30 above the source 40. The conductive member 46 is made of the same material and at the same time as the control gate 22.23 and is the output from the output circuit.

It will be appreciated that manufacturing floating gate amplifiers uses process techniques well known in the semiconductor industry.

FIG. 3 is an electrical circuit diagram of a circuit that combines the floating gate amplifier of FIG. 1 with other output circuitry, with the floating gate amplifier shown within the dashed rectangle.

The floating gate amplifier includes a MOS floating gate bias transistor 27, a MOS output i-transistor 14, a floating gate 17, and a load resistor 15. Floating gate bias transistor 27 has a drain 19 connected to a bias voltage, a source 18 connected to floating gate 17, and a gate 28 which is a control pulse line 28. The output transistor 14 has a drain 13 connected to vDD,
It has a negative II low resistor 15, a gate 12 connected to the drain 33 of the number-and-hold transistor 35, and a gate 17 which is also a floating gate 17.

In addition to the above-mentioned elements, a current source Io and a plurality of capacitors Fj C1, C2, C3, C4 are included in the amplifier circuit. Capacitor C1 represents the floating capacitance between the floating gate 17 and ground. Capacitor C2 represents the gate oxide capacitance between the floating gate and the silicon. Capacitor C3 represents the floating capacitance between the floating gate 17 and ground. The volume of the depleted silicon region between and the charge in the well m
It represents. Capacitor C4 is logical channel C
It represents the relationship between the silicon bulk substrate and the charge in the potential well for a CD.

These capacitors control the charge holding capacity of the well.

In CCD devices, information is stored in storage wells of the device. In order to read what is stored in the wells, the charge in each well must be transferred to a location where it can be read and amplified. The charge is transferred to a storage well below floating gate 17, which is an element in the floating gate capacitor. Floating gate amplifiers are non-destructive 11v read amplifiers; the charge packets in the wells are not destroyed after the information is read. This floating gate is a key feature of this amplifier. It is the gate of LIMOS output transistor 14 and is connected to the source 18 of floating gate bias transistor 27. The voltage on the floating gate first increases to υ1 as shown in the CP waveform shown at 67 in Figure 4.
1[I Turns on floating Goode bias transistor 27 by increasing the voltage on pulse line 28 and is set.

This causes the voltage ratio on floating gate 17 to be VPRES
ET, the voltage on the IIJllll pulse line 28 minus the threshold voltage of the floating gate bias transistor 27. then ill tli
The voltage on the l pulse line 28 is C, shown at 68 in FIG.
It falls like a P waveform and turns off the floating gate bias transistor 27. This allows the floating gate 17
floating gate bias transistor 27 when the upper voltage is set, the operating point of output transistor 14 is set, and a large charge packet is transferred below floating gate 17.
prevents it from turning on. Additionally, this isolates the bias voltage from the floating gate and output transistor 14. When a charge packet is transferred into the storage well below the floating gate 17, it induces a voltage on the floating gate 17, causing the already set voltage to change over time. This induced voltage is proportional to the charge in the packet. Since the current flowing through the induced voltage U output transistor 14 is changed, it can be detected and amplified. This operation is caused by the third voltage circuit of the floating gate amplifier.
This can be illustrated with reference to the figures. Wa source ■. teeth,
It represents the magnitude of the current in the electric current packet transferred to the storage well below the floating gate 17.

Therefore it is a current pulse rather than a continuous one. 1. The chain varies depending on the charge can in each charge packet. When current flows in Io, electrons are introduced into capacitors C3 and 04, causing a change in the voltage on floating gate 17 as the charge is redistributed between each capacitor.

This change in floating gate voltage changes the operating point of the q1 output transistor 14, which in turn changes the output of the floating gate amplifier as does the signal from the 94-band resistor 15. Since the floating gate amplification output is proportional to the charge in the charge packet, this mode of operation is suitable for CCD imagers.

The inventive method of operating a floating gate amplifier includes:
This can be understood with reference to FIGS. 4 and 5 as well as resetting the CCD. FIG. 4 represents the voltages applied or appearing on some of the floating gates 17, control gates 22.23 and phase electrodes 20.21 of FIG. The floating gates 17, control gates 22.23, and phase 'I1 gates 20.21 in FIG. 5 show the potentials in the gate during a typical read operation. Point 1i161.6
2 represents the potential when different voltages are supplied to each phase electrode and gate. Assume that there is a charge packet to be read in the storage well below the φ1 phase voltage ViA20. First, the charge packets in the storage 11 under floating gate 17 must be transferred to another storage well.

This means that during the time interval T, the output control G223
This can be done by increasing the voltage above and transferring the charge packet below the floating goot 17 to the well of the φ1 phase electrode 20T-. When the voltage on control gate G2 is raised, the potential below it is shown at point 1162. After the rIi load packet is transferred to the well below the phase '4 pole φ120, the voltage on control gate G2 returns to ground. The charge packet under φ2 phase electrode 21 must then be transferred to the well under floating gate 17 for reading. This is done by grounding the voltage on the φ2 phase electrode 21. That is, the 'F1 dog packet under the φ2 phase electrode 21 is thereby transferred to the input control gate 22, G, and the lower Tsukido. However, since the potential under the floating gate 17 is lower than the potential under the lll1 control gate G1, the charge packet falls into the lower part of the floating gate 17. Since the potential under the 11i+1 control gate G2 is higher than the potential under the floating gate 17, the process does not proceed any further. Transfer of this charge packet (by floating gate 1
7 and the output voltage changes proportionally.

This induced voltage is the change Δv1, Δv in the FG waveform in Fig. 4.
It can be seen as 2. As already mentioned, the voltage changes Δv1 and Δv2 differ depending on each electrical packet. After each electrically constrained packet is read, the floating gate 17
The above cable is reset as described above. In the present invention, charge packets are transferred to and from floating gate 17 using control gates 22,23. Input 11, II tm gate 22 is approximately 1.5
The output control gate 23 is held at V. It fluctuates in a pulsed manner between 0 and O volts. Human power υ1t [l gate 2
The voltage t on the φ2 phase electrode 21 does not act as a barrier to the transfer of charge packets from the storage capacitor under the φ2 phase electrode 21 when the ffill pressure is O volts. However, any charge under the floating gate 17 becomes a barrier to transfer back toward the φ2 phase electrode 21. Output control gate 23
When is O volt, it is φ1 from below floating game I-17
It becomes a barrier to the transfer of the tube packet to the phase electrode 20. However, the output control gate 23 is at V. When it is 0, charge transfer from the well of the floating gate 171 to the φ1 phase electrode 20 is allowed. The floating gate bias transistor 27 effectively sets the floating gate potential by π-
1jm+''1. Floating gate 17 is electrically connected to bias line 19 through the high and low resistors of floating gate bias transistor 27 when in the off state.

Floating gate 17 therefore remains at a constant potential PRESET, which is the voltage on control pulse line 28 minus the threshold voltage of floating gate bias transistor 27. The RC time constant determined by the shape of floating gate 17 and the resistance of off-state floating gate bias transistor 27 is very large, so that a potential can be induced on floating gate 17.

An alternative embodiment of the invention with a different device, as shown in FIGS. 6-9, includes a diode A-type transistor J3 in place of the MOS floating gate bias transistor 27 of the device shown in FIG. 70 is used. The anode 71 of this diode is connected to the floating gate 17' and the cathode to the bias line 29', both as shown in FIG. Cathode 72 is an extended region in substrate 10' of the same conductivity type as source and drain regions 112', 13 of output transistor 14'. Anode 71 is a spreading region in cathode 72 of opposite conductivity type. nTt gate 17u1 is connected to the 7 node 71 through an electrode window in the oxide layer on the anode 71 (connected to the cathode 72 through the electrode window in the oxide layer on the bias line 29'q, cathode 72, cathode 72). A thick field oxide region 31' is provided on the channel stop 32' of the same conductivity type as the substrate surrounding the substrate 72. Corresponds to the same number without a dash in the drawing.

The charge packets are read out in the same manner as already described for the floating gate biased j-transistor 27. but,! Since there is no lII1l pulse line 28, there is no resetting of the voltage on floating gate 17. This becomes clear when examining the clock sequence of the floating gate amplifier 4 using the diode embodiment, as shown in FIG. The voltage U on floating gate 17 is set to the voltage on bias line 29 by leakage current through reverse biased diode 70 . Current (yo, r
I current flows until gate 17 is charged to [LV on bias line 29]. Since floating gate 17bias is electrically connected to bias line 29 by the resistance of reverse biased diode 70, the voltage on floating gate 17 is V. , , remains set. When the floating gate voltage changes, there is only a transient period in which the charge packet is transferred to and from the 1:1 gate below the floating gate 17 and out. The floating gate capacitance and reverse bias diode 70RC time constant are very large and do not interfere with the induced voltage on the floating gate 17.

An advanced method of operating a floating gate amplifier that reduces noise induced into the system during charge transfer and clocking during voltage setting on the floating gate U1 FIGS. 10 and 1
This will be explained with reference to Figure 1.

Preferably, the floating gate amplifier shown in the first section, fA2, and FIG.
4 by directly connecting it to the source conductor 12. This modification is assumed in the following discussion.

FIG. 10 represents the voltages supplied or present at some of the gates 17, 22, 23 and phase electrodes 20, 21 of FIG. 11a. Figures 11b and 11c represent the potentials under the gate 17, 22, 23 and phase electrode 20, 21 of Figure 11a in cuts A and B in Figure 10, respectively. These potentials (as shown in FIG. Assume that there is a charge packet 50 in the storage well to be read.This charge packet 50 is shown in FIG. 11b as the hatched area below the φ,' phase electrode 20.

G2'! There is a charge packet 51 that has already been read under the lltllll gut 23. This is also indicated by diagonal hatching. This point corresponds to 8 in Figure 10, and 11
Gate 17, 22, 23 and phase electrode 20, 21 in figure a
The lower potential is as shown in Figure 11b. φ1
'For the charge packet 50 of the phase electrode to be read out,
It must be transferred below the floating gate 17.

Of course, when this charge packet 50 is transferred under the floating gate 17, the charge bucket l·51 under the 02' control gate 23 is transferred under the φ phase electrode 21. Immediately after transfer 2, the time point becomes 8 in Fig. 10, and the potentials under the goots 17, 22, 23 and phase electrodes 20, 21 in Fig. 11a become as shown in Fig. 11C.This charge transfer is realized. In order to v is the potential at which the potential begins to form.The transfer of a load bucket induces a voltage change on the floating gate 17, and the output voltage changes proportionally.This induced voltage is shown in Fig. 10. This can be seen as a change in the G waveform of Δ■1.Δ■, ΔV.Δv4.

23 As already mentioned, M pressure changes Δv1, Δ■2, Δ■.
Δv4 differs for each charge packet.

3. After a series of reads have been performed, the voltage on floating gate 17 is reset as already described.

By resetting the floating gate voltage after a series of reads rather than after reading each charge packet,
The preset vL name on floating gate 17 is decreased.

What should be noted from Fig. 10 is that φ1'. φ2 phase electrode and control gate G'. This means that changes in G2' occur at the same time. This is an important feature of this mode of operation of the amplifier, since it minimizes the synchronized clock M'fr caused by the capacitive coupling of the control gates 22, 23 to the floating gate 17. This is because this timing sequence is necessary. The homogeneous clock M-tone is minimized by
The product of the capacitance fi (C) on the 01' control gate 22 and the intensity@(Δ■,,) on the 01' control gate 22G1 is the capacitance (C) on the 02' control gate 23 and the capacitance (C) on the G2'υ1111 gate 23. faith G
2 @(Δv62〉) when the sign is changed.' That is, when the following equation is satisfied, CG1
ΔvG1" - CG2" ■G2ΔC and ΔVG2 are shown in FIG. Since the product of capacitance MkG1 and voltage is equal to charge, by satisfying this equation, ? ￥ Due to the electric charge of the opposite sign being induced on the gate 17, it becomes ? Therefore, the same phantom noise does not occur on the floating gate 17. Of course
This equation does not hold unless signals are simultaneously provided on the ν, It, +I 1ll gates 22,23. cG1
and cG2 are affected by mask level alignment, and in many cases they are not the same size. Therefore, in order to solve this result, the iIIIIII gate 22.23
You need to adjust the amplitude and offset of the above signal. When examining these waveforms in FIG. 10, it is necessary to keep the above in mind.

U
There are several advantages. The first is to eliminate the preset noise generated each time fffH on floating gate 17 is reset by resetting the voltage on floating gate 17 after a series of readings instead of doing a reset after each readout. This means that most of it can be eliminated. As already mentioned, CGIΔVGI− CG2
The control of Δvo2 eliminates clock noise caused by the capacitive coupling of control gates 22, 23 to floating gate 17. These reductions in noise result in greater device sensitivity and better resolution of the image.

Although the invention has been described with respect to illustrative embodiments, these descriptions are not intended to limit the invention thereto. It will be apparent to those skilled in the art that various modifications to the illustrated embodiment, as well as other embodiments of the invention, may be possible. Accordingly, the scope of the patent visit should be construed to include all modifications of those embodiments that fall within the true scope of the invention.

[Brief explanation of the drawing]

FIG. 1 is an enlarged plan view of a small portion of a semiconductor chip showing the physical layout of a floating gate amplifier used in the present invention. From FIG. 2a to FIG. 2d, there are 4 lines a-a. b
2 is a cross-sectional view of the amplifier of FIG. 1 along lines -b, c-c, and dd; FIG. FIG. 3 is an electrical circuit of the floating gate amplifier and other output lines of FIG. 1, with the floating gate amplifier included within the dotted line. FIG. 4 shows a clock sequence for operation of a floating gate amplifier according to the method of the invention. FIG. 5 is a potential distribution diagram of the COD near the floating gate. FIG. 6 is a partial diagram showing a modification of a portion of the floating gate amplifier of FIG. 1 in which the floating gate bias transistor is replaced with a diode. FIG. 7 is a partial view of the modified section of the cross section of FIG. 2C, illustrating the modified version of FIG. 6 in which the floating gate bias transistor has been replaced with a diode. FIG. 8 is an equivalent electrical circuit diagram of the diode portion shown in FIG. 6. FIG. 9 is a diagram illustrating a clock sequence for operation of the modified floating gate amplifier of FIG. FIG. 10 is a diagram showing a clock sequence for an alternating mode of operation of a floating gate amplifier. Figure 11a shows the floating gate near the floating gate, υII
! FIG. 3 is a circuit diagram showing an l gate and a phase electrode. FIGS. 11b and 11C are potential distribution diagrams for the CCD of FIG. 11a, showing "levels" at different times during the alternating mode of operation. ... Electron transfer channel, 12 ... Source region, 13 ... Drain region, 1
4... Output transistor, 15... Negative circulation resistance, 16
... Insulator, 17... Floating gate, 18... Source region, 19... Drain region, 20... Phase electrode, 21... Phase electrode, 22... Control gate, 23...
...Control gate, 27...Floating gate bias transistor, 28...t. lI III Valse line, 2
9... Bias line, 30... Oxide layer, 32.
...Channel stop, 33...Drain region, 3
4... Source region, 35... Sample and hold transistor, 40... Source region, 41... Drain region, 42... Sampled out sot source what transistor, 43... Conductor strip, 44
... Gate, 50 ... Charge packet, 51 ... Charge packet, 70 ... Diode, 71 ... Anode, 72 ... Cathode, 73 ... Oxide bending.

Claims (5)

[Claims] (1) In a charge-coupled device having a floating gate electrode, a control gate electrode mounted on both sides of the floating gate electrode so as to partially overlap, and first and second sets of phase electrodes, a charge packet is generated. 1. A method of operating a charge-coupled device for reading out from a charge-coupled device by transferring the charge pulses to the first and second phase electrodes, the method comprising: applying pulses alternately to first and second phase electrodes to transfer charge pulses under the phase electrodes; At that time, the series of operations of moving the charge packets under the phase electrodes in sequence, reading out each charge packet that has come under the floating gate electrode, and transferring the charge packets described above is repeated, and the charge packets are transferred under the floating gate electrode. reading said charge packets corresponding to each of the plurality of cycles that have been transferred, resetting the potential of the floating gate electrode only after the plurality of charge packets have been transferred and read out one after another, thereby resetting the potential of the floating gate electrode; Substantially reducing preset noise associated with resetting the potential of a gate electrode. (2) The method according to claim 1, wherein control gate electrodes are attached to both sides of the floating gate electrode so as to partially overlap with each other, and the control gate electrode is further provided with a charge packet to be transferred to the control gate electrode. inducing equal amounts and opposite signs of charge in floating gate electrodes to minimize the generation of synchronous clock noise. (3) transferring charge packets for readout from a charge-coupled device having a floating gate electrode, a control gate electrode partially overlying the floating gate electrode, and first and second sets of phase electrodes; The method operates by simultaneously supplying potentials that are essentially equal and separated by a voltage above and below the magnitude V_T to the control gate electrodes arranged on both sides of the floating gate electrode, respectively, and 2 phase electrodes, each with a size V_T
simultaneously supplying a potential that is larger and substantially equal to the magnitude V_T; during one series of transfer operations, the potential of the control gate electrode is simultaneously changed to be substantially equal to the magnitude V_T; and reversing the potential applied to the second phase electrode;
a potential and a magnitude V_T each substantially equal to the magnitude V_T;
transferring the charge packets by applying a larger potential; and repeating the above sequence of alternating the potentials applied to the control gate electrode and the first and second phase electrodes to move the charge packets along the charge-coupled device. and reading each charge packet as it is sent under the floating gate electrode. (4) The method of claim 3, further comprising resetting the potential of the floating gate electrode only after a plurality of charge packets have been transferred and read out under the floating gate electrode one after another, thereby resetting the potential of the floating gate electrode. A method comprising: such that preset noise associated with resetting an electrode potential is substantially reduced. (5) The method according to claim 3, wherein C_G_
1 is the capacitance of the first control gate electrode, ΔV_G_I is the signal of the same electrode during charge packet readout, and C_G_2 is the capacitance of the second control gate electrode ΔV_G_2 is the signal of the same electrode during charge packet readout. Between C_
maintaining the relationship G_1ΔV_G_1=−C_G_2ΔV_G_2, thereby minimizing the induction of equal amounts and opposite signs of charges on the floating gate electrodes and generation of synchronous clock noise thereon.