JPH031614A - Tri-state buffer circuit - Google Patents

Abstract

PURPOSE:To attain wired connection or bus connection to an output terminal of a buffer circuit and to make an output voltage level stable in a short time by providing an additional circuit provided with a leading detection circuit, an analog switch and a termination potential input terminal. CONSTITUTION:Transistors(TRs) 31-34 and components C1, C2, R1, R2, D1, D2 in an additional circuit 1 constitute a leading detection circuit 2 and TRs 35, 36 constitute an analog switch 3. When an enable control terminal EN goes to an n level from an L level, the leading detection circuit 2 detects its transition and outputs a pulse in a short time to the analog switch 3. The analog switch 3 is conductive only for a short time in the presence of the pulse input to drive an output terminal OUT at the same potential as that of a termination potential input terminal CV provided newly.

Description

[Detailed description of the invention] [Industrial application field]

The present invention is a three-state buffer circuit that can switch the state of an output terminal to three states of low impedance, low level, high level, and high impedance according to an input signal, and in particular, the output terminal changes from a low impedance state to a high impedance state. The present invention relates to a three-state buffer circuit having a function of quickly matching the potential of an output signal line to a final level when a transition occurs. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

Conventionally, output buffers of open collector, open drain, three-state type, etc. have been used to enable wired-OR connection or bus type connection. FIG. 7 shows an example in which the output terminals of a buffer circuit 41 having an open collector element 40 as an output transistor are connected to each other via a wired-OR connection signal line 48 to realize a wired-OR connection. becomes low impedance only when trying to drive its output to low level (hereinafter referred to as L level), and the high level of its output (hereinafter referred to as H level) is driven by all elements 4.
When 0 becomes high impedance, pull amplifier resistance RP
It is held by I. In this circuit, the minimum and minimum values of the pull-up resistor RPI are limited by the ability of the output transistor 40 as an open collector element, so from L level to H level, the pull-up resistor RPI, input/output elements, wiring, etc. The transition occurs only with a time constant determined by the stray capacitance C8 generated by the capacitance, and this transition causes a delay in stabilizing the output signal level (that is, the level of the signal line 48). Therefore, in Japanese Patent Application Laid-Open No. 60-182218, as shown in FIG. 8, only during the transition period when the output terminal OUT of the output transistor 40 as an open collector element transitions from the L level to the high impedance state, the data input terminal IN
The transistor 45 is turned on via the circuit 46 that differentiates the fall of the input signal to the output terminal ou'r, and the output terminal o'r is driven to the H level with low impedance, and the signal line 48 is rapidly brought to the H level.
An open collector type buffer circuit 41 has been proposed that stabilizes the voltage level.

[Problem to be solved by the invention]

However, the circuit shown in Figure 8 is a TTL type open collector circuit designed to stabilize the output terminal OUT side to the H level in a short time, and as shown in Figure 9, it uses a MOS type element. A buffer circuit 41 composed of
This method cannot be applied to a case where the impedance is stabilized at the L level when the impedance is high. Furthermore, for long-distance or high-speed signal lines, in order to prevent the generation of reflected waves due to signal level transitions, methods are used to terminate the signal line at a value close to the line impedance at the end of the signal line. In MOS level signal lines, the first
As shown in Figure 0, the power supply voltage Vcc is connected to the terminal resistor RTl,
A common method is to terminate the bus-connected output signal 53 at an intermediate potential obtained by dividing the voltage through RT2. When a conventional high-speed output element is applied to the signal line 53 that has been terminated in this manner, the voltage level on the signal line 53 at the time of transition to a high impedance state is as shown in FIG. It becomes like this. In other words, the voltage stabilization time during the high impedance period L5 is determined by the stray capacitance C5 and the terminating resistor RT1. It will be determined by RT2, so speeding up cannot be expected. Furthermore, when the L level is output during the low impedance period t3, during the transition period L4 on the way from period t3 to period t5,
This results in unnecessary high-speed, large-amplitude voltage fluctuations, which causes crosstalk, high-frequency noise, and the like. Therefore, in order to solve the above-mentioned problems, the present invention provides an external terminal for inputting a potential corresponding to the terminal potential and an output terminal that connects the external terminal only during the transition period when the output terminal transitions from a low impedance state to a high impedance state. An object of the present invention is to provide a three-state buffer circuit including a circuit that drives an output terminal with a potential equivalent to a terminal potential set at the terminal.

[Means to solve the problem]

In order to solve the above problems, the circuit of the present invention includes a data input terminal (such as IN), a control input terminal (such as enable control input terminal EN), and an output terminal (such as OUT), The output terminal is switched between a low impedance state and a high impedance state in accordance with an input logic value, and in this low impedance state,
In a three-state buffer circuit that switches the output terminal between a low level and a high level according to a logical value input to the data input terminal, an external potential input terminal (terminating potential input terminal CV, etc.) for inputting an external potential; , state change detection means for detecting a change in a logical value input to the control input terminal that switches the output terminal from a low impedance state to a high impedance state, and outputting a pulse during a transition period of switching the impedance state; a rising edge detection circuit 2, etc.), and a connection means (analog switch 3, etc.) that couples the output terminal and the external potential input terminal only during the transition period based on the pulse to match the potentials of these two terminals. Let j with and .

[For use]

During the short period when the output terminal of the 3-state converter circuit transitions from a low impedance state to a high impedance state, the terminal resistor or pull-up is output by outputting a low impedance potential equal to the termination potential set externally to the output terminal. resistance. Regardless of the value of the pull-down resistor, it becomes possible to charge the stray capacitance at high speed, and the output voltage level can be stabilized in a short period of time. Further, since this charging is performed only during a transition period when the output signal level changes, it is possible to directly connect the output terminals of the buffer circuit with a wired-OR connection or a bus connection.

【Example】

The present invention will be described in detail below with reference to FIGS. 1 to 6. FIG. 1 shows the configuration of a CMO3 type 3-state buffer circuit as an embodiment of the present invention, and FIG. 2 shows its functional block diagram. Transistors 11 to 24 in FIG. 1 constitute a conventional three-state buffer circuit, and the circuit excluding transistors 23 and 24 in the output section is as follows:
NAND gate G1 in FIG. Negative input AND game) G2
．． This is equivalent to a circuit consisting of NOT element N2. That is, in this conventional three-state buffer circuit, when the enable control input terminal EN is set to L level, the output terminal OUT is driven to a low impedance state at the same level as the data input terminal IN, and when ππ is set to H level, the input terminal OUT is driven to the low impedance state. To put the output terminal OUT in a high impedance state regardless of the state of IN. By the way, a portion 1 surrounded by a long broken line in FIGS. 1 and 2 is an additional circuit newly provided in the present invention, and in this additional circuit 1 in FIG. 1, transistors 31 to 34 and C1, C2, R1 , R2, Dl, D2 are rising edge detection (
The transistors 35 and 36 constitute the analog switch 3. Now, when the control input terminal EN changes from the L level to the H level, the rising edge detection circuit 2 detects the transition and outputs a short pulse to the analog switch 3. The analog switch 3 becomes conductive only for a short period of time when this pulse is input, and the newly provided termination potential input terminal CV
The output terminal OUT is driven at the same potential. Figure 3 is a simple symbol representation of the three-state buffer circuit in Figure 1, and the names and symbols of each terminal are the same as the first one.
Same as figure. Next, FIGS. 4 to 6 are explanatory diagrams of the operation when the three-state buffer circuit of FIG. 1 is applied to output signals at different terminal potentials, and (A) in each figure shows the circuit configuration.
Similarly, (B) shows waveforms at each terminal of this three-state buffer circuit. However, in Figures 4(A) to 6(A)
), this buffer circuit is represented by the symbol in FIG. Here, in FIG. 4, as shown in FIG. 4(A), the terminating resistor RT1.
This is an example of application to a signal line terminated at an intermediate potential by RT2, and as shown in FIG.
Except for this, it operates as a normal 3-state buffer circuit. During the periods t1 and t2 immediately after the control input terminal ■ changes from the L level to the H level, the output terminal OUT is driven with a potential equal to the termination potential inputted to the termination potential input terminal C■ as the termination potential setting signal CVa. Regardless of the presence of the stray capacitance C5, the state of the signal line can be stabilized at the short-term potential in a short time. In addition, in the same figure (B), the signal line state indicated by X indicates the state of the output signal line when a 3-state buffer circuit according to the prior art is used.
During the UT state, the part indicated by the broken line is the output terminal O.
It shows the period during which the UT is in a high impedance state. FIG. 5 shows an example of application to a signal line that is pulled-amplified via a pull-up resistor RPI, and FIG.
An example of application to a signal line pulled down via P2 is shown, but since both Figures 5 and 6 operate in the same way as Figure 4, detailed explanation is omitted here. do. Although the embodiment of the CMO3 type O3 type three-state buffer has been described above, the present invention is not limited to the CMO3 type, but can also be applied to a TTL type three-state buffer. Further, the circuit represented by the analog switch 3 can be realized by incorporating a buffer amplifier for increasing the input impedance of the termination potential input terminal C2 and controlling this amplifier circuit.

【Effect of the invention】

According to the present invention, the present invention includes a data input terminal IN, an enable control input terminal EN, and an output terminal OUT, and the output terminal OUT is set in a low impedance state and a high impedance state depending on a logical value input to the enable control input terminal EN. and in this low impedance state, an external potential is input to a three-state buffer circuit that switches the output terminal OUT between a low level and a high level according to a logic value input to the data input terminal IN. detect a change in the input logic value to the termination potential input terminal C■ for switching the output terminal OUT from a low impedance state to a high impedance state, and a rise detection circuit 2 that outputs a pulse; and an analog switch 3 that connects the output terminal OUT and the terminal potential input terminal C■ only during the transition period based on the pulse, and matches the potentials of these two terminals. Since the three-state buffer circuit of the present invention is equipped with It is possible to stabilize the potential level of the signal wire at the terminal potential in a short period of time when the output terminal of the terminal changes from a low impedance state to a high impedance state, and the level of the signal line can be determined at high speed. Furthermore, it is possible to prevent gradual changes in input voltage, which are harmful to MO8 type devices and devices that operate by detecting changes in input level, and to reduce crosstalk. It is possible to prevent the occurrence of unnecessary voltage changes that cause high frequency noise and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration as an embodiment of the present invention, FIG. 2 is a functional block diagram of FIG. 1, FIG. 3 is a diagram showing symbols for the circuit of FIG. 1, and FIGS. Fig. 6 is an explanatory diagram of different application examples of the circuit of the present invention, Figs. 7 to 9 are circuit diagrams in which buffer circuits with different open collector element configurations are wired-OR connected, and Fig. 10 is a circuit diagram in which buffer circuits with different open collector element configurations are connected in a wired-OR manner. Circuit diagram of bus, No. 11
The figure is a time chart showing changes in the voltage level of the bus when the bus of FIG. 10 is driven by a buffer circuit having a conventional high-speed oven collector element configuration. 1: Additional circuit, 2: Rise detection circuit, 3: Analog switch, C■: Termination potential input terminal, IN: Data input terminal, Iπ: Enable control input terminal, OUT: Output terminal. Figure 2 Figure 3 Figure O 8 Figure O 9

Claims (1)

[Scope of Claims] 1) A data input terminal, a control input terminal, and an output terminal, the output terminal being switched between a low impedance state and a high impedance state according to a logical value input to the control input terminal, and Under this low impedance state,
In a three-state buffer circuit that switches the output terminal between a low level and a high level according to a logical value input to the data input terminal, the external potential input terminal for inputting an external potential and the output terminal are switched from a low impedance state. a state change detection means for detecting a change in a logical value input to the control input terminal for switching to a high impedance state, and outputting a pulse during a transition period of switching the impedance state; and only during the transition period based on the pulse. A three-state buffer circuit comprising: connecting means for coupling the output terminal and the external potential input terminal to match the potentials of these two terminals.