JPH03162129A - semiconductor integrated device - Google Patents
semiconductor integrated deviceInfo
- Publication number
- JPH03162129A JPH03162129A JP1302848A JP30284889A JPH03162129A JP H03162129 A JPH03162129 A JP H03162129A JP 1302848 A JP1302848 A JP 1302848A JP 30284889 A JP30284889 A JP 30284889A JP H03162129 A JPH03162129 A JP H03162129A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- current
- semiconductor integrated
- bypass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 230000007257 malfunction Effects 0.000 abstract description 6
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 201000000390 breast intraductal proliferative lesion Diseases 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、半導体集積装置の出力回路に関し、特にデー
タ出力時の電源線に発生する電流雑音を減少させた出力
回路に関する.
〔従来の技術1
第5図は従来の半導体集積装置のCMOSの出力回路を
示す図である.14はPチャンネルMOSFETの出力
ドライバで.12はその駆動回路.15はNチャンネル
MOSFETの出力ドライバで13はその駆動回路であ
る.入力DIN.DINが共にロウレベルのときは14
.15はオフで出力端子D outはハイインピーダン
ス状態である.第6図は第5図の出力回路の動作波形の
図であり、D o u tが立下る場合を示す.DIN
がハイレベルになるとNチャンネルドライバのゲート電
圧V anはOvから■。。に立上り,Nチャンネルド
ライバの電流はピークに到達し、出力端子の電荷を放電
する.そしてD autの電圧が低下するにつれて電流
ち減少してい<.D.utが立上る場合はDINがハイ
レベルになることにより、Vapが0■になってP゛チ
ャンネルドライバを通して出力端子の電荷を充電する.
[発明が解決しようとする課題1
半導体技術の進歩と共に半導体集積装置は高速化、高集
積化が進んでいる.高速化においては出力回路の動作速
度を上げるため電流駆動力の大きい出力ドライバが使わ
れ、また高集積化が進むにつれて半導体集積装置は多く
の出力端子をもつようになってきている.この様に高速
化、高集積化が進むと出力回路が動作した時に多大な過
渡電流が流れ、集積装置内部の配線及びリードフレーム
や外部配線に存在する寄生抵抗、あるいは寄生インダク
タンスにより電源線の電圧が変動して回路の誤動作をひ
き起こす.
従来の出力回路の出力ドライバが動作し始めた時にその
電流駆動力は最大になり、急激に電源線に大きな電流が
流れるため、大きな電流ノイズが短時間に集中して発生
し回路の誤動作を起こす原因となっている。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit for a semiconductor integrated device, and more particularly to an output circuit that reduces current noise generated in a power supply line during data output. [Prior art 1] Figure 5 is a diagram showing a CMOS output circuit of a conventional semiconductor integrated device. 14 is the P-channel MOSFET output driver. 12 is its drive circuit. 15 is an output driver of the N-channel MOSFET, and 13 is its driving circuit. Input DIN. 14 when both DINs are low level
.. 15 is off and the output terminal D out is in a high impedance state. FIG. 6 is a diagram of operating waveforms of the output circuit of FIG. 5, and shows the case where D out falls. DIN
When becomes high level, the gate voltage V an of the N-channel driver changes from Ov to ■. . The current of the N-channel driver reaches its peak and discharges the charge at the output terminal. As the voltage of Dout decreases, the current decreases. D. When ut rises, DIN becomes high level, Vap becomes 0, and the output terminal is charged through the P channel driver. [Problem to be solved by the invention 1] As semiconductor technology advances, semiconductor integrated devices are becoming faster and more highly integrated. In order to increase the operating speed of output circuits, output drivers with large current driving power are used in order to increase the operating speed of output circuits, and as the degree of integration increases, semiconductor integrated devices are beginning to have many output terminals. As speed increases and integration increases, a large amount of transient current flows when the output circuit operates, and the voltage of the power supply line due to parasitic resistance or inductance existing in the wiring inside the integrated device, the lead frame, and the external wiring. fluctuates, causing circuit malfunction. When the output driver of a conventional output circuit starts operating, its current driving power reaches its maximum, and a large current suddenly flows through the power supply line, causing large current noise to be concentrated in a short period of time, causing circuit malfunction. It is the cause.
特に前記の現象は,出力ドライバをオン抵抗の小さなバ
イポーラトランジスタで形成した場合には顕著になる.
本発明はこのような問題点を解決するためになされたち
ので、ピーク電流及び電流の時間変化率すなわち電流ノ
イズを滅少させて回路の誤動作を起こさない半導体集積
装置を提供することを目的とする。The above phenomenon is particularly noticeable when the output driver is formed from a bipolar transistor with low on-resistance. The present invention has been made to solve these problems, and therefore, it is an object of the present invention to provide a semiconductor integrated device that reduces peak current and the time rate of change of current, that is, current noise, and does not cause circuit malfunction. .
[課題を解決するための手段1
本発明の半導体集積装置は、トーテムポールに形成され
たバイポーラ出力ドライバに駆動電流を提供する出力ド
ライバ駆動回路において、出力ドライバに供給するベー
ス電流を制限する電流制限回路と、該電流制限回路と並
列接続され電流制限の機能を停止するバイパス回路と前
記バイパス回路を出力の変化によって動作させる帰還回
路を備えたことを特徴とする。[Means for Solving the Problems 1] The semiconductor integrated device of the present invention has a current limiter that limits the base current supplied to the output driver in an output driver drive circuit that provides drive current to a bipolar output driver formed in a totem pole. The present invention is characterized in that it includes a circuit, a bypass circuit connected in parallel with the current limiting circuit to stop the current limiting function, and a feedback circuit that operates the bypass circuit according to a change in output.
[実 施 例〕 以下本発明の実施例を図面を用いて説明する。[Example〕 Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明の実施例に係る出力回路を示すものであ
る.NPNバイポーラトランジスタlの駆動回路は、ダ
イオードとPチャンネルMOSFETを直列接続した電
流制限回路5と、PチャンネルMOSFETによるバイ
パス回路6が含まれており,6は前段の電圧■。が変化
した後、遅れ?動作するようにD 6utからの帰還回
路7の出力信号によって制御される.第2図に帰還回路
7を示す.本実施例ではNPNバイポーラトランジスタ
1及び3のショート電流を防ぐためD++i信号と論理
をとっている.またD。、の立ち上りを受けてバイパス
回路6をONする様になっている為、第2図中のインバ
ータのロジックレベルを変えることによってバイパス回
路6のONタイミングを変えることができる.またNP
Nバイポーラトランジスタ3の駆動回路は,ダイオード
とPチャンネルMOSFETを直列接続した電流制限回
路8と,PチャンネルMOSFETによるバイパス回路
9が含まれており、9は前段の■2が変化した後、遅れ
て動作するようにD outからの帰還回路10の出力
信号によって制御される.第3図に帰還回路10を示す
.本実施例ではNPNバイポーラトランジスタ1及び3
のショート電流を防ぐためDIN信号と論理をとってい
る.またD.■の立ち下りを受けてバイパス回路9をO
Nする様になっている為、第3図中のネガティブAND
のロジックレベルを変えることによってバイパス回路9
のONタイミングを変えることができる.次に第4図の
波形をもとに第1図の回路の動作を説明する*DINが
Lレベルになると第1図のV0が立上り5を通してV
6aの電圧は上昇する。FIG. 1 shows an output circuit according to an embodiment of the present invention. The drive circuit for the NPN bipolar transistor 1 includes a current limiting circuit 5 in which a diode and a P-channel MOSFET are connected in series, and a bypass circuit 6 using a P-channel MOSFET, where 6 is the voltage of the previous stage. Delay after changes? The operation is controlled by the output signal of the feedback circuit 7 from D6ut. Figure 2 shows the feedback circuit 7. In this embodiment, in order to prevent short-circuit current in NPN bipolar transistors 1 and 3, logic is established with the D++i signal. D again. Since the bypass circuit 6 is turned ON in response to the rise of , the ON timing of the bypass circuit 6 can be changed by changing the logic level of the inverter shown in FIG. Also NP
The drive circuit for the N bipolar transistor 3 includes a current limiting circuit 8 in which a diode and a P-channel MOSFET are connected in series, and a bypass circuit 9 using a P-channel MOSFET. The operation is controlled by the output signal of the feedback circuit 10 from D out. Figure 3 shows the feedback circuit 10. In this embodiment, NPN bipolar transistors 1 and 3
It is logically connected to the DIN signal to prevent short-circuit current. Also D. In response to the falling of ■, the bypass circuit 9 is turned to O.
Since it is designed to be N, the negative AND in Figure 3
bypass circuit 9 by changing the logic level of
The ON timing of can be changed. Next, we will explain the operation of the circuit in Figure 1 based on the waveforms in Figure 4. *When DIN goes to L level, V0 in Figure 1 rises and passes through 5 to V
The voltage at 6a increases.
ここで■1はまだHレベルであるため6はオフでアル.
従ってV。はVD0VBtになる.V0.のLレベルか
ら中間電位への変化を受けて7による遅延時間△tの後
にv1がLレベルになると6はオンし再び上昇しほぼV
0に到達する.この時電流制限回路5を流れる電流はほ
とんどゼロとなる.従ってNPNバイポーラトランジス
タのベース電圧を前記の様に制御することにより、lを
流れる電流を制限することができる。つまり、lを流れ
る電流ハv。7!+5VoIll−v.EノトキハI1
テ制限され、V0。のときはピーク電流I2が流れる.
よって出力ドライバ1のピーク電流が押さえられると同
時に電流の時間変化率が小さくなる.D INが立下っ
て出力D outが立下る時、V abは当初V。.−
■.まで立上り、Δtの後にV outに到達する.3
を流れる電流は第4図に示す様に■,とI,の段階に分
かれる.
[発明の効果]
以上述べてきた様に本発明の出力回路は、出力ドライバ
の電流を動作初期において制限し、出力信号変化を受け
て上記制限を解くため、最大電流値及び電流の時間変化
率を小さくでき、電源線の電圧変動を低減させて回路の
誤動作を防ぐという効果がある.Here, ■1 is still at H level, so 6 is off and Al.
Therefore V. becomes VD0VBt. V0. When v1 becomes L level after a delay time △t due to 7 due to the change from L level to intermediate potential, 6 turns on and rises again to approximately V
Reach 0. At this time, the current flowing through the current limiting circuit 5 becomes almost zero. Therefore, by controlling the base voltage of the NPN bipolar transistor as described above, the current flowing through l can be limited. In other words, the current flowing through l is v. 7! +5VoIll-v. E notokiha I1
Te is limited and V0. When , peak current I2 flows.
Therefore, the peak current of the output driver 1 is suppressed, and at the same time, the time rate of change of the current is reduced. When D IN falls and the output D out falls, V ab is initially V. .. −
■. Vout is reached after Δt. 3
The current flowing through is divided into stages ■ and I, as shown in Figure 4. [Effects of the Invention] As described above, the output circuit of the present invention limits the current of the output driver at the initial stage of operation, and releases the above limitation in response to a change in the output signal. This has the effect of reducing voltage fluctuations in the power supply line and preventing circuit malfunctions.
第1図は本発明の一実施例を示す出力回路図、第2図は
第1図の出力帰還回路7の一例を示す図、第3図は第1
図中の出力帰還回路10の一例を示す図、第4図は第l
図の動作波形を示す図.第5図は従来の出力回路を示す
図.第6図は第5図の動作波形を示す図.
1、3・・・・NPNバイポーラ出力ドライ2 ・
4、
5、
6、
7、
1 4 ・
l 5 ・
l 2、
DIN・
D..,
V da)
V ap、
VO ・
■1 ,
1 3 ・
D1.4・
v,!1.
Vdll・
■1
■, ・
・ダイオード
・抵抗
・電流制限回路
・バイパス回路
・出力帰還回路
・Pチャンネル出力ドライバ
・Nチャンネル出力ドライバ
・駆動回路
・出力回路相補入力信号
・出力回路出力信号
・出力ドライバ駆動信号電圧
・・電流制御回路入力信号電圧
・・パイバス回路入力信号電圧
以
上1 is an output circuit diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of the output feedback circuit 7 of FIG. 1, and FIG. 3 is a diagram showing an example of the output feedback circuit 7 of FIG.
A diagram showing an example of the output feedback circuit 10 in the figure, FIG.
A diagram showing the operating waveforms in the figure. Figure 5 shows a conventional output circuit. Figure 6 is a diagram showing the operating waveforms of Figure 5. 1, 3...NPN bipolar output dryer 2, 4, 5, 6, 7, 1 4, l 5, l 2, DIN, D. .. , V da) V ap, VO ・ ■1 , 1 3 ・ D1.4・ v,! 1. Vdll・ ■1 ■, ・Diode・Resistor・Current limit circuit・Bypass circuit・Output feedback circuit・P channel output driver・N channel output driver・Drive circuit・Output circuit complementary input signal・Output circuit output signal・Output driver drive Signal voltage: Current control circuit input signal voltage: Pibus circuit input signal voltage or higher
Claims (1)
駆動電流を供給する出力ドライバ駆動回路において、出
力ドライバに供給するベース電流を制限する電流制限回
路と、該電流制限回路と並列接続され電流制限の機能を
停止するバイパス回路と、前記バイパス回路を出力の変
化によって動作させる帰還回路を備えたことを特徴とす
る半導体集積装置。In an output driver drive circuit that supplies drive current to a bipolar output driver formed in a totem pole, there is a current limit circuit that limits the base current supplied to the output driver, and a current limit circuit that is connected in parallel with the current limit circuit to stop the current limit function. 1. A semiconductor integrated device comprising: a bypass circuit that operates the bypass circuit; and a feedback circuit that operates the bypass circuit based on a change in output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1302848A JPH03162129A (en) | 1989-11-21 | 1989-11-21 | semiconductor integrated device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1302848A JPH03162129A (en) | 1989-11-21 | 1989-11-21 | semiconductor integrated device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03162129A true JPH03162129A (en) | 1991-07-12 |
Family
ID=17913826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1302848A Pending JPH03162129A (en) | 1989-11-21 | 1989-11-21 | semiconductor integrated device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03162129A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009118478A (en) * | 2007-10-29 | 2009-05-28 | Itt Manufacturing Enterprises Inc | Radiation hardened logic circuits |
-
1989
- 1989-11-21 JP JP1302848A patent/JPH03162129A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009118478A (en) * | 2007-10-29 | 2009-05-28 | Itt Manufacturing Enterprises Inc | Radiation hardened logic circuits |
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