JPH0316319A - encoder circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention (9) relates to an encoder circuit for a semiconductor electronic circuit.

2. Description of the Related Art As an example of a conventional encoder circuit, FIG. 3 shows a 2-bit matrix type encoder circuit of an A/D converter. In the same figure, l is the power supply voltage 2 is the constant current 3 to 5
The emitter of transistor 3 is connected to bit line 6, the emitter of transistor 4 is connected to bit line 7, and the emitter of transistor 5 is connected to both bit lines 6 and 7. However, in the encoder circuit configured as described above, if the bit line 6 is the lower bit and the bit line 7 is the upper bit, then for example, when a signal is input to the base input of the transistor 3 (the friend bit line 6 Since the potential of transistor 4 rises to high level and bit line 7 is low level, the output of encoder 4 is (01).Similarly, transistor 4
When the input is input to the transistor 5, the output is (10), and when the input is input to the transistor 5, the output is (11). However, the problem to be solved by the invention is that in an encoder circuit having the above-mentioned structure, {Friend: A scene where the number of bits of coding has increased
In layout design, the bit line becomes quite long, which causes a large wiring capacitance load and slows down the coding speed. It is determined by the capacitance of the bit line and the current drawn into the bit line.In general, when the capacitance of the bit line becomes large, the rise time is Although the coding time often depends on the fall time, if the current of current source 2 has to be increased from 1 to speed up the fall time of the potential, the power consumption will increase.

In view of these points, the present invention aims to provide an encoder circuit that can reduce power consumption and reduce coding time.Means for Solving the ProblemsThe present invention has been made to solve the above problems by reducing the number of bits. In a matrix encoder circuit having a bit line according to the bit line, a driving means for driving the bit line, and a constant current source for flowing a current through the bit line, a clock pulse for operating the driving means; The device is equipped with a clock-controlled current source that increases the current flowing through the bit line in synchronization with the clock pulse.

According to the above-described structure, the present invention increases the current value of the bit line only when necessary, thereby speeding up the potential fall time and increasing the coding speed without unnecessarily increasing power consumption. Embodiment (Embodiment 1) FIG. 1 shows a 2-bit encoder circuit of an A/D converter in the first embodiment of the present invention.
is a clock-controlled current source, and the other components are the same as those in FIG. 3, so the same components are given the same numbers and detailed explanations will be omitted. The operation of the encoder circuit of this embodiment constructed as described above will be described below.

The time when the human power is switched to this encoder circuit using the clock of the entire system is called the through time, and the time when the input is confirmed is called the latching time. In synchronization with this clock, the clock-controlled current source 81 is controlled so that a current flows ON when it is through, and it is turned OFF when it is latched. Therefore, at the time of through (Dai (a) When the potential of the bit line falls, the current value of the constant current source 2 is IS, the current value when the clock controlled current source 8 is ON is I c, and the load capacitance of the bit line is C I ), then the time T1 required to lower the potential difference Vd is Tt=Cb-Vd/(Is+Ic), and the time TO required when there is no clock-controlled current source as in the conventional example is TO=Cb-Vd /Is Therefore, To-T1=Cb-Vd{Ic/(Is(Is+
I c))) will be faster.

(b) When the bit line potential rises, the rise time of the bit line potential does not depend on the current value of the constant current source 2, but mainly depends on the performance of the driving transistors 3 to 5. Negative effects of the present invention 11'Io (C) When the potential of the bit line is held In this case, only the current flowed by the clock controlled current source 8 from 3 to 5 has no effect on the potential of the bit line. Also, when latching, the clock control current source 8 is OFF.
In addition, in the conventional example, the current value of the constant current source 2 is set to Is + Ic ('L).
Even when latching, an additional current flows by Ic, increasing power consumption (Embodiment 2) Fig. 2 shows a 2-bit encoder circuit of an A/D converter in a second embodiment of the present invention. 9 is an input signal discriminating circuit configured with a logic circuit for discriminating the input signal of the encoder (output of the comparator) and switching the clock-controlled current source. The same numbers are given to the same structural parts and detailed explanations are omitted.The operation of the encoder circuit of this embodiment constructed as above will be explained below. A NOR circuit for determining the input signal to line 6.7 and an AND for switching the clock-controlled current source 8 from its output and the clock signal.
Even if you remove it from the circuit, when the clock signal is 1, it is a through time, and when it is 0, it is a latch time. When the clock is O! The output of the 1AND circuit is 0 regardless of the output of the NOR circuit.
Therefore, the clock controlled current source 8 does not operate at 1,%.
When the clock is 1, the clock-controlled current source 8 operates only when the output of the NOR circuit is 1, that is, the input to the encoder circuit (output of the comparator) is 0.
When the input to the encoder is 1, the clock-controlled current source 8 does not operate (for example, the signal l to the transistor 4
When the signal O is input to transistors 3 and 5, the potential of bit line 7 becomes 1 and the potential of bit line 6 becomes O. ) to the NOR circuit becomes (10) and the output becomes O. The clock-controlled current source 8 connected to the bit line 7 does not operate. The input is (00) and the output is 1
When the clock is 1 (table), the clock-controlled current source 8 connected to the bit line 6 operates and the bit line 6
In Embodiment 1 (above), all clock-controlled current sources 8 are operated at the time of through. Current also flows through the bit lines that do not need to lower the potential, which reduces the speed. There is no problem with power consumption, although power consumption is wasted due to unnecessary current. In the second embodiment, the bit line that does not need to be lowered in potential is determined and the clock-controlled current source connected to that bit line is turned off. In terms of speed, the effect is the same as that of the first embodiment, and the power consumption can be saved. Effects of the Invention As is clear from the above explanation, the present invention can reduce the speed of an encoder circuit with a large number of bits without increasing the power consumption. can be increased with as little as possible, and its practical effects are significant.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a circuit diagram of an encoder circuit according to a first embodiment of the present invention. Fig. 2 is a circuit diagram of an encoder circuit according to a second embodiment of the present invention. Fig. 3 is a circuit diagram of a conventional encoder circuit. In the circuit diagram of the circuit ■...Power supply ff. 2... Constant current fL 3~5...
・Bi-bolar NPN transistor length 6, 7... Bit for coding 8... Clock control current? f9
%9...Input signal discrimination circuit

Claims (2)

[Claims] (1) In a matrix encoder circuit having a bit line according to the number of bits, a driving means for driving the bit line, and a constant current source for flowing a current through the bit line, a clock pulse for operating the driving means; An encoder circuit comprising a clock-controlled current source that increases a current flowing through the bit line in synchronization with the clock pulse. (2) The encoder circuit according to claim 1, further comprising discriminating means for discriminating the input signal to the driving means for driving the bit line and switching the clock-controlled current source.