JPH031633A - Transmission/reception buffer management system for packet switching circuit - Google Patents

Abstract

PURPOSE:To quicken the processing of packet switching by using an associative memory and applying buffer management control to a transmission/reception buffer. CONSTITUTION:Transmission control sections 7-9 make the request of a transmission packet to its own channel to an associative memory control section 5 as soon as its own channel is idle. The associative memory control section 5 gives an input to an associative memory section 4 and the address number of a coincident data is obtained as an output data. A transmission/reception buffer number obtained in such a manner is informed the transmission control sections 7-9 and the address of the transmission/reception buffer is obtained from the transmission/reception buffer number and the packet sent to an output channel. When the transmission is finished and a reply is obtained from the opposite party, an open request is given to the associative memory control section 5 to rewrite the operating state display of the associative memory section 4.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a transmitting/receiving buffer management method for a packet switching circuit, and particularly to a packet switching method in which received packets from a plurality of input channels are temporarily stored in a transmitting/receiving buffer memory shared by each channel. This paper relates to a management method for transmitting and receiving buffers in circuits.

[Conventional technology]

Conventionally, the management of the transmission and reception buffers in this type of packet switch circuit has been controlled by software, which manages empty transmission and reception buffers, allocates them to empty input channels, and designates these transmission and reception buffers upon completion of packet reception. A series of controls is performed in which the buffer is connected to the transmission queue of the transmitted transmission signal, waits for an empty transmission channel, and then activates the transmission of this buffer on the transmission channel.

[Problem that the invention seeks to solve]

Since the transmission/reception buffer management method of the conventional packet switching circuit described above is controlled by software, buffer management control such as buffer search is determined by the processing capacity of the processing device, which has the disadvantage of suppressing the speedup of packet switching. .

[Means for solving problems]

The transmitting/receiving buffer management method of the packet switching circuit of the present invention has a plurality of input/output channels, and a transmitting/receiving buffer having a plurality of transmitting/receiving buffers, which is composed of a random access memory shared by each channel and once receives a received packet from each input channel. In a packet switching circuit that stores packets in a memory and then transmits them to an output channel, a buffer usage status indication, an output channel number of the written packet, and a transmission sequence number of the packet for this output channel correspond to the transmitting/receiving buffer. and an associative memory control means that searches for an empty transmission/reception buffer and searches for a transmission packet of each output channel by collating each content of the associative memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. This is a transmission control section. As shown in FIG. 2, the associative memory unit 4 stores the usage status (empty) of a buffer corresponding to each of the plurality of transmitting and receiving buffers included in the transmitting and receiving buffer memory unit 6.

The output channel number and transmission sequence number of the received packet are stored in this buffer. The reception control units 1 to 3 request the associative memory control unit 5 to allocate an empty buffer when they do not have an empty transmitting/receiving buffer at the time of initial setting or after completion of bat reception. As shown in FIG. 3, the associative memory control unit 5 blanks out the buffer usage status display for search data (=0 in the figure), masks other data, inputs it to the associative memory unit 4, and sends and receives it as a search result. Obtain the address output of matching data corresponding to the buffer number. FIG. 4 is an explanatory diagram showing the storage contents of the associative memory unit 4 and the search process. As shown in FIG. One of them is automatically selected in the associative memory and output. The transmitting/receiving buffer number selected in this way is notified to the receiving control units 1 to 3 that have made the request, and the buffer usage status for the stored data in the associative memory unit 4 is notified to the associative memory controlling unit 4. It is rewritten to receive status B (=1 in the figure). Next, the reception control units 1 to 3 find the address of the corresponding transmission/reception buffer in the transmission/reception buffer memory unit 6 based on the notified transmission/reception buffer number, and write the received packet into the buffer upon receiving the packet. Then, upon completion of reception, the reception control unit 1
3 requests the associative memory control unit 5 to rewrite the buffer usage state display to the reception complete state and to register the output channel number, and the associative memory control unit 5 rewrites the corresponding data in the associative memory unit 4 (= in the figure). 2) The data of the transmission sequence number for the output channel managed by the associative memory control unit 5 is rewritten.

The above is a description of the 0th-order transmission side operation, which is the operation from the transmission/reception buffer search to the completion of packet reception.

The transmission control units 7 to 9 request the associative memory control unit 5 to transmit packets for their own channel as soon as their own channel becomes vacant. In accordance with this request, the content addressable memory control unit 5 sets the content addressable memory unit 4 to display the buffer usage status of the search data in the reception complete state, the output channel number to the requested channel number, and the transmission sequence number, as shown in FIG. The transmission sequence number of this channel is set and input to the associative memory section 4, and the address number of matching data corresponding to the transmission/reception buffer number is obtained as output data. FIG. 6 is an explanatory diagram showing the storage contents of the associative memory unit 4 and the search process in this case. If there is no transmission packet for this channel, an output without matching data is obtained. However, if there is no matching data, the associative memory control unit 5 periodically repeats this search until matching data is obtained. The transmission/reception buffer number obtained in this way is notified to the transmission control units 7 to 9, and the transmission control unit that receives the notification calculates the address of the transmission/reception buffer in the transmission/reception buffer memory unit 6 from the transmission/reception buffer number, and outputs the packet of this transmission/reception buffer. When transmission to the channel 6 is completed, or when retransmission control is being performed, a request is issued to the associative memory control unit 5 to release the transmission/reception buffer when a response is received from the partner station.

In accordance with this request, the associative memory control section 5 rewrites the buffer usage state display of the corresponding data in the associative memory section 4 to an empty state.

〔Effect of the invention〕

As explained above, the present invention uses content addressable memory to perform buffer management control for transmitting and receiving buffers.
Buffer management control, which was conventionally performed by software, is realized by hardware logic, which has the effect of speeding up packet switching processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an arrangement diagram of stored data in an associative memory, FIG. 3 is an arrangement diagram of search data for checking free space in the transmitting/receiving buffer, and FIG. 5 is an explanatory diagram showing the content stored in the associative memory and the search process, FIG. 5 is an array diagram of search data for searching the sending/receiving buffer to be sent, and FIG. 6 is the content stored in the content addressable memory and the search process during transmission. FIG. 1-3... Reception control unit, 4... Associative memory unit, 5.
. . . Content addressable memory control unit, 6 . . . Transmission/reception buffer memory unit, 7 to 9 . . . Transmission control unit.

Claims (1)

[Claims] A packet switching circuit that has multiple input/output channels and stores received packets from each input channel in a transmit/receive buffer memory that is composed of random access memory shared by each channel and has multiple transmit/receive buffers, and then transmits them to an output channel. an associative memory that stores, corresponding to the transmission/reception buffer, an indication of the usage status of the buffer, an output channel number of the written packet, and a transmission sequence number of the packet to this output channel, and each content of this associative memory. 1. A transmitting/receiving buffer management method for a packet switching circuit, comprising associative memory control means for searching for an empty transmitting/receiving buffer and searching for transmitting packets of each output channel by collating.