JPH03165526A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To avoid increase in the parasitic capacity between gate and source of a MESFET for enhancing the high-frequency characteristics by a method wherein an insulating layer for T type gate electrode formation is prevented from being left on an active layer. CONSTITUTION:An n type active layer 102, n<+>type ohmic contact forming layers 103, a source electrode 104, a drain electrode 105 are formed on a GaAs substrate 101, successively the first insulating layer e.g. an SiO2 layer 11 and then the second insulating layer e.g. a silicon nitride layer 12 are laminated-thereon. Next, a photoresist layer 13 is laminated on the silicon nitride layer 12, an opening 13a of the gate length is made in a prospective gate electrode formation region further to make another opening 12a by vertically etching the silicon nitride layer 12 exposed in the opening 13a. Next, the side etching process is performed until the SiO2 layer as the first insulating layer 11 on the active layer 102 from the source electrode 104 to the drain electrode 105 is completely removed from the region on the active layer 102. At this time, since the etching rate of the silicon nitride layer as the second insulating layer to ammonium fluoride water solution is about 1/10 of the SiO2 layer as the first insulating layer, the silicon nitride layer as the second layer is hardly etched away.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a field effect transistor,
It is particularly applied to a method of manufacturing a field effect transistor having a T-shaped gate electrode.

(Prior Art) Among field effect transistors, a mechanical gate field effect transistor (hereinafter abbreviated as MESFET) has excellent high frequency characteristics and is therefore widely used in microwave communication equipment.

In order to improve the high frequency characteristics of such MESFETs, it is necessary to shorten the gate length and reduce the gate resistance. MESFETs having T-shaped gate electrodes are being developed.

An example of a conventional manufacturing method of a MESFET having a T-type gate electrode will be described below with reference to FIGS. 2(a) to 2(e). First, ions are implanted into a GaAs substrate 101 to form an n-type active layer 102 and an n4'' type ohmic contact formation layer 103 (FIG. 2(a)). Next, a lift-off method is used to form a resource electrode 104. After forming a drain electrode 105 on the n+ type ohmic contact forming layer 103, alloying treatment by heating is performed (FIG. 2(b)). □Layer 106. A photoresist layer 107 is laminated and formed, and this photoresist layer 107 is patterned to form an opening 1078 in the area where the gate electrode is to be formed.
06 is subjected to reactive ion etching (RIB) and vertically etched to form an opening 1 in the layer 106.
06a (FIG. 2(c)), and the opening 1078 of the resist layer 107 is further expanded to form an opening 107b (FIG. 2(d)). Then, for example, aluminum is used as a gate electrode forming metal. A T-shaped gate electrode 108 is formed by vapor deposition over the entire surface and a lift-off method (FIG. 2(e)).

(Problems to be Solved by the Invention) The method for manufacturing the MESFET having the T-type gate electrode described above has the following problems. First, although the method of etching the insulating layer using RIE can faithfully transfer the dimensions of the resist layer, it has the disadvantage of damaging the n-type active layer and deteriorating the high frequency characteristics.
If there is an insulating layer on the eaves of the gate electrode, there is a problem in that high frequency characteristics are degraded through an increase in parasitic capacitance between the gate and the source. In addition, if there is a thick insulating layer on the n-type active layer, the stress of the thick insulating layer will cause the ME
There is also the problem that the high frequency characteristics of the SFET are degraded.

Since the above two problems can be resolved by removing the thick insulating layer, it is conceivable to completely remove the insulating layer by, for example, chemical dry etching using CF4 (Freon) gas. However, in this case, there is a problem that the aluminum layer of the gate electrode is exposed to the CF4 plasma for a long time, and the high frequency characteristics are deteriorated due to damage caused by the plasma.

An object of the present invention is to provide an improved manufacturing method for eliminating the adverse effects of the insulating layer for forming the T-type gate electrode in the conventional MESFET manufacturing method.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a field effect transistor according to the present invention includes the steps of forming a semiconductor active layer on a semi-insulating semiconductor substrate;
a step of sequentially laminating a first insulating layer and a second insulating layer having a lower etching rate than the first insulating layer after forming a source electrode and a drain electrode on the semiconductor active layer; A step of laminating a resist layer, and forming an opening with a desired gate length in the resist layer, forming an opening in the second insulating layer using the resist layer as a mask, and then connecting the source electrode to the second insulating layer through the opening. A step of removing the first insulating layer between the drain electrodes, a step of further widening the opening in the resist layer, and a step of depositing a metal film for a gate electrode using the resist layer as a mask and forming a T-shaped gate by a lift-off method. This includes the step of forming electrodes.

(Function) In the MESFET manufacturing method described above, since no insulating layer for forming the T-type gate electrode remains on the active layer, high frequency characteristics are improved and the reproducibility of the T-type gate formation process is also excellent.

(Example) An example of the present invention will be described below with reference to the drawings. In the description, parts that are the same as in the prior art will be shown in the drawings with the same reference numerals as in the prior art, and some of the conventional steps and drawings will be used and the explanation will be omitted.

Following the steps illustrated in FIGS. 2(a) and 2(b) of forming an n-type active layer 102, an n1-type ohmic contact formation layer 103, a source electrode 104, and a drain electrode 105 on a GaAs substrate 101, One of the first insulating layers, for example, a layer 11 of Sin, is formed with cvo2 to about 3,000 yen.
The insulating layer, for example, the silicon nitride layer 12, is subjected to plasma CVD.
It is formed by laminating approximately 2,000 sheets using the D method (Fig. 1 (
a)).

Next, a photoresist layer 13 is laminated on the silicon nitride layer 12 of the second insulating layer, and an opening 13a having the gate length is provided in the region where the gate electrode is to be formed, and the silicon nitride layer 12 exposed here is Etching is performed vertically using reactive ion etching (RIE) using CF4 gas and 02 gas to form openings 12a.

This opening 12a and the opening 13a of the Sin2 layer have approximately the same diameter and communicate directly with each other. Next, the first insulating layer 1 is formed on the active layer 102 from the source electrode 104 to the drain electrode 105.
Side etching is performed using, for example, an ammonium fluoride aqueous solution until the Si2 layer of No. 1 is completely removed from above the active layer region (FIG. 1(b)). At this time, the silicon nitride layer that is the second insulating layer is Since the etching rate of the layer in the ammonium fluoride aqueous solution is about 1/10 of that of the first insulating layer, the silicon nitride layer, the second insulating layer, the silicon nitride layer, is hardly etched. The active layer of is not damaged by RIE.

Next, using the electron beam exposure method or the light exposure method again, the apertures 13a of the resist layer are further enlarged.
b (Fig. 1(C)).

Next, a gate electrode metal such as aluminum is deposited on the entire surface to a thickness of about 8,000 yen, and a T-shaped gate electrode 14 is formed by a lift-off method (FIG. 1(d)).

In the above embodiments, an ion-implanted MESFET has been described, but it goes without saying that it is also effective for general MESFETs.

The material is not limited to silicon nitride, and for example, a phosphosilicate glass (PSG) layer or an aluminum oxide (Al2O) layer may be used. Furthermore, it is also effective when etching the first insulating layer by a predetermined recess width, performing recess etching, and then removing all of the first insulating layer between the source electrode and the drain electrode.

〔Effect of the invention〕

As described above, according to the present invention, since no insulating layer for forming a T-type gate electrode remains on the active layer, ME! 5F
This is a field effect transistor that does not increase the parasitic capacitance between the gate and source of the ET, and because the active layer is not damaged by RIE, it not only has improved high frequency characteristics but also has excellent reproducibility in the manufacturing process. can provide a manufacturing method.

[Brief explanation of the drawing]

FIGS. 1(a) to d) show an MES according to an embodiment of the present invention.
The FET manufacturing method is shown in the order of steps.
Figures (a) to (e) are sectional views showing the conventional manufacturing method of MESFET in the order of steps. 101-GaAs substrate, 102-n-type active layer, 103.
...N+ type ohmic contact forming layer. 104...source electrode, 105...drain electrode-
11... First insulating layer (Sin, layer). 12... second insulating layer (silicon nitride layer), 13...
- Photoresist layer, 14... gate electrode.

Claims (1)

[Claims] A step of forming a semiconductor active layer on a semi-insulating semiconductor substrate, and after forming a source electrode and a drain electrode on the semiconductor active layer, forming a first insulating layer and a second insulating layer having a lower etching rate than the first insulating layer. a step of laminating a resist layer on the second insulating layer; and a step of laminating a resist layer on the second insulating layer; and after forming an opening with a desired gate length in the resist layer, applying the resist layer to the second insulating layer using the resist layer as a mask. A step of forming an opening and further removing the first insulating layer between the source electrode and the drain electrode through the opening, a step of further widening the opening of the resist layer, and a step of forming a gate using the resist layer as a mask. A method for manufacturing a field effect transistor, including a step of depositing a metal film for an electrode and forming a T-shaped gate electrode by a lift-off method.